Optimizing {CNN} model inference on {CPUs}

Y Liu, Y Wang, R Yu, M Li, V Sharma… - 2019 USENIX Annual …, 2019 - usenix.org
The popularity of Convolutional Neural Network (CNN) models and the ubiquity of CPUs
imply that better performance of CNN model inference on CPUs can deliver significant gain …

Survey on combinatorial register allocation and instruction scheduling

RC Lozano, C Schulte - ACM Computing Surveys (CSUR), 2019 - dl.acm.org
Register allocation (mapping variables to processor registers or memory) and instruction
scheduling (reordering instructions to increase instruction-level parallelism) are essential …

Register allocation by puzzle solving

FM Quintão Pereira, J Palsberg - Proceedings of the 29th ACM SIGPLAN …, 2008 - dl.acm.org
We show that register allocation can be viewed as solving a collection of puzzles. We model
the register file as a puzzle board and the program variables as puzzle pieces; pre-coloring …

Optimal DNN primitive selection with partitioned boolean quadratic programming

A Anderson, D Gregg - … of the 2018 International Symposium on Code …, 2018 - dl.acm.org
Deep Neural Networks (DNNs) require very large amounts of computation, and many
different algorithms have been proposed to implement their most expensive layers, each of …

Rl4real: Reinforcement learning for register allocation

S VenkataKeerthy, S Jain, A Kundu… - Proceedings of the …, 2023 - dl.acm.org
We aim to automate decades of research and experience in register allocation, leveraging
machine learning. We tackle this problem by embedding a multi-agent reinforcement …

Solving pbqp-based register allocation using deep reinforcement learning

M Kim, JK Park, SM Moon - 2022 IEEE/ACM International …, 2022 - ieeexplore.ieee.org
Irregularly structured registers are hard to abstract and allocate. Partitioned Boolean
quadratic programming (PBQP) is a useful abstraction to represent complex register …

Generalized instruction selection using SSA-graphs

D Ebner, F Brandner, B Scholz, A Krall… - Proceedings of the …, 2008 - dl.acm.org
Instruction selection is a well-studied compiler phase that translates the compiler's
intermediate representation of programs to a sequence of target-dependent machine …

User devices cooperating to support resource aggregation

C Carter, R Kravets - Proceedings Fourth IEEE Workshop on …, 2002 - ieeexplore.ieee.org
MOPED (MObile grouPEd Device) is a network model that treats a user's set of personal
devices as a single, virtual device. The nodes of the MOPED dynamically aggregate …

Optimal register allocation in polynomial time

PK Krause - … Construction: 22nd International Conference, CC 2013 …, 2013 - Springer
A graph-coloring register allocator that optimally allocates registers for structured programs
in polynomial time is presented. It can handle register aliasing. The assignment of registers …

Optimal and heuristic global code motion for minimal spilling

G Barany, A Krall - … Construction: 22nd International Conference, CC 2013 …, 2013 - Springer
The interaction of register allocation and instruction scheduling is a well-studied problem:
Certain ways of arranging instructions within basic blocks reduce overlaps of live ranges …