A novel balanced ternary adder using recharged semi-floating gate devices

H Gundersen, Y Berg - … on Multiple-Valued Logic (ISMVL'06), 2006 - ieeexplore.ieee.org
This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with
Recharged Semi-Floating Gate Devices. By using balanced ternary notation, it possible to …

Fast addition using balanced ternary counters designed with CMOS semi-floating gate devices

H Gundersen, Y Berg - … on Multiple-Valued Logic (ISMVL'07), 2007 - ieeexplore.ieee.org
This paper presents ternary counters using balanced ternary notation. The balanced ternary
counters can replace binary full adders or counters in fast adder structures. The circuits use …

Cellular automata: Reversibility, semi-reversibility and randomness

K Bhattacharjee - arXiv preprint arXiv:1911.03609, 2019 - arxiv.org
In this dissertation, we study two of the global properties of 1-dimensional cellular automata
(CAs) under periodic boundary condition, namely, reversibility and randomness. To address …

A 90µm× 64µm225μW class-AB CMOS differential flipped voltage follower with output driving capability up to 100 pF

C Muñiz-Montero, LA Sánchez-Gaspariano… - Microelectronics …, 2013 - Elsevier
A compact differential flipped voltage follower (DFVF) with low power consumption, capable
to deliver currents several orders of magnitude larger than its quiescent current and with …

A balanced ternary multiplication circuit using recharged semi-floating gate devices

H Gundersen, Y Berg - 2006 NORCHIP, 2006 - ieeexplore.ieee.org
This paper presents a multiplier circuit using balanced ternary (BT) notation. The multiplier
can multiply both negative and positive numbers, which is one of the advantage able …

[PDF][PDF] Aspect of balanced ternary arithmetic implemented using CMOS recharged semi-floating gate device

H Gundersen - Oslo: Oslo University, 2008 - researchgate.net
Mostly all electronics used in computers today are based on binary logic. However, does the
binary logic have the capacity to be the leading technology in the future? Thus I raise the …

A novel ternary switching element using CMOS recharge semi floating-gate devices

H Gundersen, R Jensen, Y Berg - … International Symposium on …, 2005 - ieeexplore.ieee.org
In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG)
ternary switching element. The design is applicable for reconstructing or refreshing ternary …

Proposal for a bidirectional gate using pseudo floating-gate

O Mirmotahari, Y Berg - 4th IEEE International Symposium on …, 2008 - ieeexplore.ieee.org
In this paper we propose a bidirectional logic gate. The advantages of this gate lie in the use
of floating-gate, thus making the gate operate on voltage variations across capacitors. We …

[PDF][PDF] Teaching production line balancing with an interactive, simulation-based training system

BW Mazziotti, FB Armstrong, KA Powell Jr - Proceedings of the 25th …, 1993 - dl.acm.org
From 1980 to 1992 textile and apparel imports to the US increased more than 250%.
Foreign manufacturers have labor rates that are fractions of the US standards and …

[PDF][PDF] On the potential of cmos recharged semi-floating gate devices used in balanced ternary logic

H Gundersen - Proceedings of the 17th International Workshop on …, 2008 - Citeseer
Most of the electronic circuits designed today use binary logic. However, will binary logic be
the leading technology in the future, why not uses balanced ternary logic, implemented …