A low-voltage/swing clocking methodology is developed through both circuit and algorithmic
innovations. The primary objective is to significantly reduce the power consumed by the …

A low-swing clocking methodology is introduced to achieve low-power operation at 20nm
FinFET technology. Low-swing clock trees are used in existing methodologies in order to …

This paper presents a new current source model (CSM) that allows to model noise on supply
nets originating from CMOS logic cells. It also captures the influence of dynamic supply …

A macromodeling technique for digital cells is presented. The proposed macromodel allows
fast and accurate signal approximation, as well as delay estimation for CMOS digital circuits …

State-of-the-art timing tools are built around the use of current source models (CSMs), which
have proven to be fast and accurate in enabling the analysis of large circuits. As circuits …

It is formidable to embed iterative simulations into the clock tree synthesis process to verify
the skew and slew constraints. Instead, accurate and simple timing models for clock buffers …

Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-
level models for standard cells, which have accuracy problems as well as require massive …

Cloud Computing offers application developers an abstract view of computational resources
that can be provisioned on demand over a computer network. This model allows …

This paper introduces a methodology that optimizes the performance of a low swing clock
tree under a skew bound. Low-swing clock trees are preferred for a reduction in the clock …

To increase the accuracy of static timing analysis, the traditional nonlinear delay models
(NLDMs) are increasingly replaced by the more physical current source models (CSMs) …