Coarse-grained reconfigurable architectures for radio baseband processing: A survey

Z Hassan, A Ometov, ES Lohan, J Nurmi - Journal of Systems Architecture, 2024 - Elsevier
Emerging communication technologies, such as 5G and beyond, have introduced diverse
requirements that demand high performance and energy efficiency at all levels …

Peak: A single source of truth for hardware design and verification

C Donovick, J Melchert, R Daly, L Truong… - ACM Transactions on …, 2023 - dl.acm.org
Domain-specific languages for hardware can significantly enhance designer productivity,
but sometimes at the cost of ease of verification. On the other hand, ISA specification …

Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication

KY Chen, T Mason Nelson, A Khadem… - ACM Transactions on …, 2024 - dl.acm.org
Stream processing, which involves real-time computation of data as it is created or received,
is vital for various applications, specifically wireless communication. The evolving protocols …

Efficiently Synthesizing a Complete Set of Unique Instruction Selection Rewrite Rules Using SMT

R Daly - 2024 - search.proquest.com
With the ever-evolving landscape of computer architecture, we are witnessing an influx of
novel intermediate representations (IRs) and instruction set architectures (ISAs). These …

Efficient Coarse-Grained Reconfigurable Array architecture for machine learning applications in space using DARE65T library platform

L Zulberti, M Monopoli, P Nannipieri, S Moranti… - Microprocessors and …, 2025 - Elsevier
With the increasing use of satellites, rovers, and other space exploration devices, Artificial
Intelligence (AI) is also becoming an important tool for space exploration, allowing …

ICED: An Integrated CGRA Framework Enabling DVFS-Aware Acceleration

C Tan, M Jiang, D Patil, Y Ou, Z Li, L Ju… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
Coarse-grained reconfigurable arrays (CGRAs) are a promising solution to enable energy-
efficient acceleration of applications from different domains. By leveraging reconfiguration at …

Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study

N Taheri, S Tabrizchi, A Roohi - Micromachines, 2024 - mdpi.com
This paper conducts a comprehensive study on intermittent computing within IoT
environments, emphasizing the interplay between different dataflows—row, weight, and …

DFModel: Design Space Optimization of Large-Scale Systems Exploiting Dataflow Mappings

S Ko, N Zhang, O Hsu, A Pedram… - arXiv preprint arXiv …, 2024 - arxiv.org
We propose DFModel, a modeling framework for mapping dataflow computation graphs
onto large-scale systems. Mapping a workload to a system requires optimizing dataflow …

Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning

Z Li, C Yin, TK Bandara, R Juneja, C Tan, Z Bai… - arXiv preprint arXiv …, 2024 - arxiv.org
Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that
enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape …

Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection

R Daly, C Donovick, C Terrill, J Melchert… - arXiv preprint arXiv …, 2024 - arxiv.org
Compiling programs to an instruction set architecture (ISA) requires a set of rewrite rules that
map patterns consisting of compiler instructions to patterns consisting of ISA instructions. We …