Multi-layer integrated circuits having isolation cells for layer testing and related methods

K Chakrabarty, R Wang - US Patent 10,338,133, 2019 - Google Patents
Multi-layer integrated circuits having isolation cells for layer testing and related methods are
disclosed. According to an aspect, an integrated circuit includes first and second layers that …

Multi-layer integrated circuits having isolation cells for layer testing and related methods

K Chakrabarty, R Wang - US Patent 10,838,003, 2020 - Google Patents
Multi-layer integrated circuits having isolation cells for layer testing and related methods are
disclosed. According to an aspect, an integrated circuit includes multiple isolation cells …

Circuit and Architecture Optimization Techniques for Emerging Technologies of High-Speed Computing

박희천 - 2018 - s-space.snu.ac.kr
For system-on-chip (SoC) design improvement in more-than-Moore scale, entirely new high-
speed computing technologies beyond conventional optimizations are often proposed. They …