This paper presents a hybrid design of flash based successive approximation register (SAR)
analog-to-digital converter (ADC) with a resolution of 6 bits, operating at 1 GS/s. The …

A charge sharing technique for high-speed double-tail comparators is presented. This
technique is applied to the pre-amplifier stage of the dynamic comparators so that the …

A typical dynamic comparator consists of two stages A first stage comprising a differential
amplifier and a second stage comprising latch-based circuitry. The primary function of the …

A high speed, high resolution and low power comparator is designed and analyzed in this
work. The proposed comparator is designed in low power TSMC 65 nm CMOS technology …

This study presents a fully differential dynamic comparator with low kickback noise, an effect
caused by voltage variations in the regeneration nodes of these types of circuit. Given their …

In low power electronics technology, a lot of new technology has already been introduced to
reduce the power consumption of comparator. This paper presents the comparative study of …

This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an
inverter based high-speed comparator, including the design of common-mode body biasing …

A dynamic comparator usually has two stages; differential amplifier as stage 1 and latch-
based circuitry as stage 2. A differential amplifier amplifies the difference in the input …

Comparator is an important building blocks used in analog-to-digital converters. Its function
is to compare two analog inputs and delivers a logic value at the output. In this project an …

Analog design provides substantial portfolio for low power comparators switching at GHz
ranges. In this paper, we have tendered a novel 12-Transistor dynamic analog comparator …