Design of 64-bit Signed Magnitude Comparator using FPGA for IoT applications

VLSI Implementation of an Efficient 2D Median Finding Algorithm for Non Linear Image Filtering

K Vasanth, MC Nithin, SD ALN… - … on Circuit Power …, 2024 - ieeexplore.ieee.org
This paper proposes an efficient architecture of two dimensional (2-D) Modified shear
sorting architecture which produces median output based on pixels given in a window of MX …
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