A blockchain-based traceable IP copyright protection algorithm

L Xiao, W Huang, Y Xie, W Xiao, KC Li - IEEE Access, 2020 - ieeexplore.ieee.org
Current Intellectual Property (IP) copyright protection technologies have low efficiency of
authority management, traceability, and scalability. In this work, a blockchain-based IP …

Reconfigurable FIR filter using distributed arithmetic on FPGAs

M Kumm, K Möller, P Zipf - 2013 IEEE International Symposium …, 2013 - ieeexplore.ieee.org
An architecture for a dynamically run-time reconfigurable finite impulse response (FIR) filter
is presented in this work. It is based on distributed arithmetic (DA) combined with a look-up …

Parallel distributed arithmetic FIR filter design based on 4: 2 compressors on Xilinx FPGAs

X Zhang, L Tu, D Chen, Y Yuan… - 2017 4th International …, 2017 - ieeexplore.ieee.org
Distributed arithmetic (DA) algorithm is widely used for finite impulse response (FIR) filter
implementation. In the beginning, DA was proposed as sequential DA (SDA), and then was …

Low power systolic array based digital filter for DSP applications

S Karthick, S Valarmathy… - The Scientific World …, 2015 - Wiley Online Library
Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in
digital form to estimate characteristic parameter of a signal into a desirable form. This paper …

Performance Analysis and Optimization of Distributed Arithmetic-Based Convolutional Algorithms for FIR Filters on FPGA

C Chen, V Romashchenko… - 2023 34th Irish …, 2023 - ieeexplore.ieee.org
Distributed arithmetic (DA) implementation for finite impulse response (FIR) filters on field-
programmable gate arrays (FPGAs) is highly desirable in digital signal processing due to its …

Techniques for efficient implementation of fir and particle filtering

SA Alam - 2016 - diva-portal.org
Finite-length impulse response (FIR) filters occupy a central place many signal processing
applications which either alter the shape, frequency or the sampling frequency of the signal …

Design of distributed arithmetic based reconfigurable filters

M Sandhya, E Senthilkumar… - 2016 IEEE Annual India …, 2016 - ieeexplore.ieee.org
Digital signal processing techniques are widely used for a large number of applications with
digital filters being considered as one of the basic elements. Digital filter design involves …

Low Power FPGA Implementation of an Efficient AES-SBOX Realization for Health Care Applications

ESS Priya, L Suganthi - 2023 - researchsquare.com
In present digital world, the data transmitted over network has become worldwide. The
information compiled, processed and communicated in Bits and bytes of digital format over …

Lut saving in embedded fpgas for cache locking in real-time systems

A Martí Campoy, F Rodríguez Ballester… - … Journal On Advances …, 2013 - riunet.upv.es
[EN] In recent years, cache locking have appeared as a solution to ease the schedulability
analysis of real-time systems using cache memories maintaining, at the same time, similar …

Design Automation and Case Studies

A Palchaudhuri, RS Chakraborty… - … Integer Arithmetic Circuit …, 2016 - Springer
All the architectures proposed in the previous chapters have been realized using the bit-
sliced design paradigm. The architectures are very regular in their structures, thereby …