Variations in nanometer CMOS flip-flops: Part I—Impact of process variations on timing
In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops
(FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The …
(FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The …
Two novel low power and very high speed pulse triggered flip‐flops
R Razmdideh, M Saneei - International Journal of Circuit …, 2015 - Wiley Online Library
Two novel low power and high‐speed pulse triggered flip‐flops were presented in this
paper. Short circuit current was controlled, and race condition between pull‐up and pull …
paper. Short circuit current was controlled, and race condition between pull‐up and pull …
Analysis and comparison of variations in double edge triggered flip-flops
In this paper, the impact of variations on the most representative double-edge triggered flip-
flop (FF) topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly …
flop (FF) topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly …
New design of scan flip-flop to increase speed and reduce power consumption
In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented,
in which short circuit current is controlled. Switching activity is decreased to reduce the …
in which short circuit current is controlled. Switching activity is decreased to reduce the …
Comparative analysis of the robustness of master-slave flip-flops against variations
In this paper, the variation of performance and robustness against hold time violations are
investigated for various representative Master-Slave flip-flops. The analysis explicitly …
investigated for various representative Master-Slave flip-flops. The analysis explicitly …
[PDF][PDF] A Two-Dimensional Extensible Bus Technology and Protocol for VLSI Processor Core
LC Eng - mro.massey.ac.nz
Intellectual property (IP) core design modularity and reuse in Very-Large-Scale-Integration
(VLSI) silicon have been the key focus areas in design productivity improvement in order to …
(VLSI) silicon have been the key focus areas in design productivity improvement in order to …
Implementation-based design fingerprinting for robust IC fraud detection
With the global spanning of integrated circuit (IC) and electronic device supply chains, the
ability of an untrusted foundry to alter a design for intellectual property (IP)/IC piracy …
ability of an untrusted foundry to alter a design for intellectual property (IP)/IC piracy …
A two-dimensional extensible bus technology and protocol for VLSI processor core: a thesis presented in partial fulfilment of the requirements for the degree of Master …
CE Loke - 2011 - mro.massey.ac.nz
Intellectual property (IP) core design modularity and reuse in Very-Large-Scale-Integration
(VLSI) silicon have been the key focus areas in design productivity improvement in order to …
(VLSI) silicon have been the key focus areas in design productivity improvement in order to …