A high memory bandwidth fpga accelerator for sparse matrix-vector multiplication
Sparse matrix-vector multiplication (SMVM) is a crucial primitive used in a variety of scientific
and commercial applications. Despite having significant parallelism, SMVM is a challenging …
and commercial applications. Despite having significant parallelism, SMVM is a challenging …
Ultralow-latency hardware-in-the-loop platform for rapid validation of power electronics designs
D Majstorovic, I Celanovic, ND Teslic… - IEEE Transactions …, 2011 - ieeexplore.ieee.org
This paper introduces a unified approach to the validation of power-electronics (PE) control
hardware, firmware, and software designs. It is based on a scalable application-specific …
hardware, firmware, and software designs. It is based on a scalable application-specific …
Optimized data reuse via reordering for sparse matrix-vector multiplication on fpgas
Sparse matrix-vector multiplication (SpMV) is of paramount importance in both scientific and
engineering applications. The main workload of SpMV is multiplications between randomly …
engineering applications. The main workload of SpMV is multiplications between randomly …
An energy efficient column-major backend for FPGA SpMV accelerators
Y Umuroglu, M Jahre - 2014 IEEE 32nd International …, 2014 - ieeexplore.ieee.org
FPGAs are promising candidates for energy efficient acceleration of sparse matrix-vector
multiplication (SpMV), a kernel with important applications in scientific computing and …
multiplication (SpMV), a kernel with important applications in scientific computing and …
A high-speed floating-point multiply-accumulator based on fpgas
B Zhou, G Wang, G Jie, Q Liu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed.
It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC) …
It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC) …
Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression
Sparse matrix–vector multiplication (SpMV) on FPGAs has gained much attention. The
performance of SpMV is mainly determined by the number of multiplications between …
performance of SpMV is mainly determined by the number of multiplications between …
Redesk: A reconfigurable dataflow engine for sparse kernels on heterogeneous platforms
Sparse Matrix-Vector Multiplication (SpMV) is the most important sparse linear algebra
kernel in both scientific and engineering applications. Due to its irregular control flow and …
kernel in both scientific and engineering applications. Due to its irregular control flow and …
A conflict-free scheduler for high-performance graph processing on multi-pipeline FPGAs
FPGA-based graph processing accelerators are nowadays equipped with multiple pipelines
for hardware acceleration of graph computations. However, their multi-pipeline efficiency …
for hardware acceleration of graph computations. However, their multi-pipeline efficiency …
Modular design of fully pipelined reduction circuits on FPGAs
Fast and efficient reduction circuits are critical for a broad range of scientific and embedded
system applications. High throughput reduction circuits are typically hand designed for …
system applications. High throughput reduction circuits are typically hand designed for …
A practical measure of FPGA floating point acceleration for High Performance Computing
JD Cappello, D Strenski - 2013 IEEE 24th International …, 2013 - ieeexplore.ieee.org
A key enabler for Field Programmable Gate Arrays (FPGAs) in High Performance Computing
(HPC) has been the addition of hard arithmetic cores. These “slices of DSP” dedicated to …
(HPC) has been the addition of hard arithmetic cores. These “slices of DSP” dedicated to …