This paper presents a fast and effective approach to gate-version selection and threshold
voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load …

Modern electronic design automation flows depend on both implementation and signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …

The objective of a leakage recovery step is to make use of positive slack and reduce power
by performing appropriate standard-cell swaps such as threshold-voltage (Vth) or channel …

Accurate delay analysis with distributed RC delay can be computationally expensive, and
can contribute the majority of the total runtime for gate sizers. Recent works have shown that …

Modern high-performance System-on-Chip (SoC) design flows highly depend on signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …

For many years, discrete gate sizing has been widely used for timing and power optimization
in VLSI designs. The importance of gate sizing optimization has been emphasized by …

We propose techniques to achieve very fast multi-threaded gate-sizing and threshold-
voltage swap for leakage power minimization. We focus on multi-threading Lagrangian …

Engineering change order (ECO) plays an important role in design flow to perform leakage
optimization with gate-sizing and assignment approaches. Unfortunately, it is extremely time …

Static power consumption is a critical challenge for IC designs, particularly for mobile and
IoT applications. A final post-layout step in modern design flows involves a leakage recovery …

Timing closure remains one of the most critical challenges of a physical synthesis flow,
especially when the design operates under multiple operating conditions. Even if timing is …