High-level synthesis for FPGAs: From prototyping to deployment

J Cong, B Liu, S Neuendorffer… - … on Computer-Aided …, 2011 - ieeexplore.ieee.org
Escalating system-on-chip design complexity is pushing the design community to raise the
level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of …

Recent developments in high-level synthesis

YL Lin - ACM Transactions on Design Automation of Electronic …, 1997 - dl.acm.org
We survey recent developments in high level synthesis technology for VLSI design. The
need for higher-level design automation tools are discussed first. We then describe some …

Force-directed algorithms for schematic drawings and placement: A survey

SH Cheong, YW Si - Information Visualization, 2020 - journals.sagepub.com
Force-directed algorithms have been developed over the last 50 years and used in many
application fields, including information visualisation, biological network visualisation …

An approach for quantitative analysis of application-specific dataflow architectures

B Kienhuis, E Deprettere, K Vissers… - Proceedings IEEE …, 1997 - ieeexplore.ieee.org
In this paper we present an approach for quantitative analysis of application-specific
dataflow architectures. The approach allows the designer to rate design alternatives in a …

[图书][B] Hardware/software co-design: principles and practice

J Staunstrup, W Wolf - 2013 - books.google.com
Introduction to Hardware-Software Co-Design presents a number of issues of fundamental
importance for the design of integrated hardware software products such as embedded …

[图书][B] The synthesis approach to digital system design

P Michel, U Lauther, P Duzy - 1992 - books.google.com
Over the past decade there has been a dramatic change in the role played by design
automation for electronic systems. Ten years ago, integrated circuit (IC) designers were …

Control flow and memory management optimization

F Franssen, M Van Swaaij, L Nachtergaele… - US Patent …, 2000 - Google Patents
Selected code is modeled in a polyhedral dependency graph (PDG). A placement optimizer
maps each element of the PDG to an optimally placed PDG. An ordering optimizer maps the …

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

P Sikka, AR Asati, C Shekhar - Microprocessors and Microsystems, 2021 - Elsevier
Harris corner detection is an algorithm frequently used in image processing and computer
vision applications to detect corners in an input image. In most modern applications of image …

High-level DSP synthesis using concurrent transformations, scheduling, and allocation

CY Wang, KK Parhi - … on Computer-Aided Design of Integrated …, 1995 - ieeexplore.ieee.org
This paper addresses high-level synthesis methodologies for dedicated digital signal
processing (DSP) architectures used in the iterative Loop-based Minnesota Architecture …

Speed optimal FPGA implementation of the encryption algorithms for telecom applications

P Sikka, AR Asati, C Shekhar - Microprocessors and Microsystems, 2020 - Elsevier
The last two decades have seen a revolution in telecom technology with the evolution of
three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to …