The goals of this study are:(i) to compare Linux kernel (2.4. 22) behavior under a broad
range of errors on two target processors—the Intel Pentium 4 (P4) running RedHat Linux 9.0 …

This study presents a theoretical throughput analysis of two buffered-crossbar switches,
called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are …

The memory size required for a combined input and crosspoint queued (CICQ) switch with
an existing credit-based flow control is proportional to the flow control latency between the …

The amount of memory in buffered crossbars is proportional to the number of crosspoints, or
O (N/sup 2/), where N is the number of ports, and to the crosspoint buffer size, which is …

Buffered crossbars with virtual output queuing are considered an alternative to bufferless
crossbars mainly because the latter requires a complex global scheduling algorithm that …

A multi-cabinet implementation of a combined input and crosspoint queued (CICQ) switch
introduces a large RTT latency between the line cards and switch fabric, requiring a large …

The performance of Internet routers is greatly defined by the adopted switch architecture.
Combined input-crosspoint buffered (CICB) packet switches are being considered of …

A buffered crossbar supporting P priorities and a flow control latency of RT packets between
the input adapter and the crossbar requires a memory of order O (N/sup 2/* P* RT) packets …

Combined input-crosspoint buffered (CICB) switches can achieve high switching
performance without speedup. However, the dedicated crosspoint buffers in a CICB switch …

The amount of memory in buffered crossbars in combined input-crosspoint buffered switches
is proportional to the number of crosspoints, or O (N/sup 2/), where N is the number of ports …