“Satisfiability (SAT) related topics have attracted researchers from various disciplines: logic,
applied areas such as planning, scheduling, operations research and combinatorial …

One of the most important industrial applications of SAT is currently Bounded Model
Checking (BMC). This technique is typically used for formal hardware verification in the …

We describe a method for using abstraction to reduce the complexity of temporal-logic
model checking. Using techniques similar to those involved in abstract interpretation, we …

In this paper, we discuss the use of binary decision diagrams to represent general matrices.
We demonstrate that binary decision diagrams are an efficient representation for every …

In recent years, formal methods have emerged as an alternative approach to ensuring the
quality and correctness of hardware designs, overcoming some of the limitations of …

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is
modified to represent state graphs using binary decision diagrams (BDD's) and partitioned …

This paper describes a new BDD-based logic optimization system, BDS. It is based on a
recently developed theory for BDD-based logic decomposition, which supports both …

Implicit invocation or publish-subscribe has become an important architectural style for large-
scale system design and evolution. The publish-subscribe style facilitates developing large …

In this paper we describe the ForSpec Temporal Logic (FTL), the new temporal property-
specification logic of ForSpec, Intel's new formal specification language. The key features of …

Formal Equivalence Checking and Design Debugging covers two major topics in design
verification: logic equivalence checking and design debugging. The first part of the book …