Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier

P Anguraj, T Krishnan - Analog Integrated Circuits and Signal Processing, 2021 - Springer
Decimal multiplication is the most common operation in arithmetic applications. This paper
presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded …

A Single Electron Transistor-Based Floating Point Multiplier Realization at Room Temperature Operation

S Banik, R Trivedi, A Kalavadiya, Y Agrawal… - … Technology Trends in …, 2022 - Springer
Floating point numbers provide more range as compared to the fixed point values. The
multiplier is one of the main blocks of a processor. For improved performance, there is a …

Investigation on Performance of Single Precision Floating Point Multiplier (SPFPM) Using CSA Multiplier and Different Types of Adders

H Amjad, Z Ahmad, M Abrar, H Rasheed - Engineering Proceedings, 2022 - mdpi.com
Nowadays, floating point multiplier (FPM) plays an essential role in computers. The IEEE
754 norm for floating point numbers is the most widely recognized portrayal for real numbers …

Design of area efficient unified binary/decimal adder/subtractor using triple carry based prefix adder

T Krishnan, P Anguraj, S Saravanan… - 2022 8th …, 2022 - ieeexplore.ieee.org
Arithmetic operations of the binary numbers play a vital role in the design of General
Purpose Processors (GPP), Arithmetic Logic Units (ALU), etc. Similarly, decimal addition and …

Design and Implementation of RISC-V Based Pipelined Multiplier

R Sun, H Liu, R Zhang, J Qu - Journal of Physics: Conference …, 2023 - iopscience.iop.org
Among the many microprocessors, RISC-V as an open-source instruction set is gradually
gaining popularity among academia and industry. The performance of the multiplier in the …

Design and Implementation of High Frequency 16-bit full adder on FPGA Families

P Puneeth, AS Raghuvanshi… - 2023 4th International …, 2023 - ieeexplore.ieee.org
An adder serves as the main structural component of any contemporary ALU-based
processor. It is known that addition is a very fundamental operation that is utilized in almost …

Design of 32-bit Floating Point Multiplier for FPGA

X Zhang, DI Kim - The Journal of the Korea institute of electronic …, 2024 - koreascience.kr
With the expansion of floating-point operation requirements for fast high-speed data signal
processing and logic operations, the speed of the floating-point operation unit is the key to …

[PDF][PDF] Design Efficient Vedic-Multiplier for Floating-Point MAC Module

FT Hussein, FK AL-Assfor - 2024 - ijeee.edu.iq
Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing
(DSP) applications, such as image convolution and filters, especially when performed on …

Implementation of EOG Denoising IIR Filter on FPGA

GEO PG, DR Bai J - … of the International Conference on Systems …, 2022 - papers.ssrn.com
The electrical activity caused by the corneo-retinal standing potential due to eyeball
movement is known as an electrooculogram (EOG). EOG is useful in many medical …

Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT

H Yang, H Chen, Y Fu, L Li - 2021 18th International SoC …, 2021 - ieeexplore.ieee.org
The current multiplication and division IP imple-mentation are mainly achieved through LUT-
based and iterative methods. This paper proposes a new hardware architecture, for fast …