Efficient implementation of fast redundant number adders for long word-lengths in FPGAs

W Kamp, A Bainbridge-Smith… - … Conference on Field …, 2009 - ieeexplore.ieee.org
The use of redundant number systems can significantly improve computational performance
in numerically intensive applications, however, the implementation of their arithmetic circuits …

A flexible DSP block to enhance FPGA arithmetic performance

H Parandeh-Afshar, A Cevrero… - … Conference on Field …, 2009 - ieeexplore.ieee.org
We propose a new DSP block for use in modern high-performance FPGAs. Current DSP
blocks contain fixed-bitwidth multipliers that can be combined efficiently to form larger …

Managing the complexity in embedded and cyber-physical system design: system modeling and design-space exploration

SH Attarzadeh Niaki - 2014 - diva-portal.org
To cope with the increasing complexity of embedded and cyber-physical system design,
different system-level design approaches are proposed which start from abstract models and …

Redundant Number Systems for Optimising Digital Signal Processing Performance in Field Programmable Gate Array

WHM Kamp - 2010 - ir.canterbury.ac.nz
Speeding up addition is the key to faster digital signal processing (DSP). This can be
achieved by exploiting the properties of redundant number systems. Their expanded symbol …

Uso eficiente de aritmética redundante en FPGAs

MA Ortiz - 2013 - helvia.uco.es
Hasta hace pocos años, la utilización de aritmética redundante en FPGAs había sido
descartada por dos razones principalmente. En primer lugar, por el buen rendimiento que …

[HTML][HTML] Uso eficiente de aritmética redundante en fpgas

MAO López - 2013 - dialnet.unirioja.es
RESUMEN DE LA TESIS DOCTORAL DE D. MANUEL AGUSTÍN ORTIZ LÓPEZ El resumen
de la tesis para la base de datos Teseo debe ser una presentación de la tesis y tener la …