[PDF][PDF] Modeling and verification of network-on-chip using constrained-DEVS

S Gholami, HS Sarjoughian - … of the Symposium on Theory of …, 2017 - academia.edu
Verification of models is necessary for some classes of systems to guarantee safety
properties in addition to satisfying functional requirements. Exhaustive model checking is a …

Action-level real-time network-on-chip modeling

S Gholami, HS Sarjoughian - Simulation Modelling Practice and Theory, 2017 - Elsevier
To simulate time-constrained operations and scheduling for Network-on-Chip (NoC)
systems, we introduce a new set of component specifications at flit level grounded in Action …

NoC simulation modeling in DEVS-suite

H Ahmadinejad, F Refan, HS Sarjoughian - Proceedings of the 2011 …, 2011 - dl.acm.org
Study of Network-on-Chip (NoC) systems requires simulators capable of handling their
unique characteristics. Toward this objective, a set of simulation models are developed …

[PDF][PDF] VERIFICATION OF CONSTRAINED-DEVS NETWORK-ON-CHIP MODELS

S Gholami, HS Sarjoughian - sce.carleton.ca
Verification of models is necessary for some classes of systems to guarantee safety
properties in addition to satisfying functional requirements. Exhaustive model checking is a …

Hybrid Multiresolution Simulation & Model Checking: Network-On-Chip Systems

S Gholami - 2017 - keep.lib.asu.edu
Designers employ a variety of modeling theories and methodologies to create functional
models of discrete network systems. These dynamical models are evaluated using …

[PDF][PDF] NoC-DEVS Simulator

H Ahmadinejad, F Refan, HS Sarjoughian - academia.edu
Abstract Study of Network-on-Chip (NoC) systems requires simulators capable of handling
their unique characteristics. Toward this objective, a set of simulation models are developed …