ABC: An academic industrial-strength verification tool

R Brayton, A Mishchenko - … Conference, CAV 2010, Edinburgh, UK, July …, 2010 - Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic
circuits appearing in synchronous hardware designs. ABC combines scalable logic …

[图书][B] Electronic design automation: synthesis, verification, and test

LT Wang, YW Chang, KTT Cheng - 2009 - books.google.com
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

High throughput FIR filter architectures using retiming and modified CSLA based adders

P Patali… - IET Circuits, Devices & …, 2019 - Wiley Online Library
A methodology to improve the throughput of FIR filters through the effective use of retiming
and efficient add–multiply operation is presented in this study. Delay, energy and area …

Scalable and scalably-verifiable sequential synthesis

A Mishchenko, M Case, R Brayton… - 2008 IEEE/ACM …, 2008 - ieeexplore.ieee.org
This paper describes an efficient implementation of sequential synthesis that uses induction
to detect and merge sequentially-equivalent nodes. State-encoding, scan chains, and test …

A microeconomic model for hierarchical bandwidth sharing in dynamic spectrum access networks

D Niyato, E Hossain - IEEE Transactions on Computers, 2010 - ieeexplore.ieee.org
We consider the problem of hierarchical bandwidth sharing in dynamic spectrum access (or
cognitive radio) environment. In the system model under consideration, licensed service (ie …

High throughput and energy efficient linear phase FIR filter architectures

P Patali, ST Kassim - Microprocessors and Microsystems, 2021 - Elsevier
High throughput, low complex and energy efficient linear phase FIR filter structures with low
latency are highly desirable for most of the portable signal processing applications …

Logic synthesis in a nutshell

JHR Jiang, S Devadas - Electronic Design Automation, 2009 - Elsevier
Publisher Summary Logic synthesis is the process of automatic production of logic
components, in particular digital circuits. It is a subject about how to abstract and represent …

Robust QBF encodings for sequential circuits with applications to verification, debug, and test

H Mangassarian, A Veneris… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Formal CAD tools operate on mathematical models describing the sequential behavior of a
VLSI design. With the growing size and state-space of modern digital hardware designs, the …

Minimization of mealy finite-state machines by using the values of the output variables for state assignment

VV Solov'ev - Journal of Computer and Systems Sciences …, 2017 - Springer
Structural models of finite-state machines (FSMs) that make it possible to use the values of
the output variables for encoding the internal states are studied. To minimize the area (the …

High throughput and energy efficient FIR filter architectures using retiming and two level pipelining

P Patali, ST Kassim - Procedia Computer Science, 2020 - Elsevier
A methodology to improve the throughput and energy efficiency of finite impulse response
(FIR) filters through the effective application of retiming and two-level pipelining is presented …