Magnetic racetrack memory: From physics to the cusp of applications within a decade

R Bläsing, AA Khan, PC Filippou, C Garg… - Proceedings of the …, 2020 - ieeexplore.ieee.org
Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the
potential to overcome fundamental constraints of existing memory and storage devices. It is …

Leveraging transverse reads to correct alignment faults in domain wall memories

S Ollivier, D Kline, R Kawsher… - 2019 49th Annual …, 2019 - ieeexplore.ieee.org
Spintronic domain wall memories (DWMs) are prone to alignment faults, which cannot be
protected by traditional error correction techniques. To solve this problem, we propose a …

Transverse-read-codes for domain wall memories

YM Chee, A Vardy, E Yaakobi - IEEE Journal on Selected …, 2023 - ieeexplore.ieee.org
Transverse-read is a novel technique to detect the number of '1's stored in a domain wall
memory, also known as racetrack memory, without shifting any domains. Motivated by the …

Locally-constrained de Bruijn codes: Properties, enumeration, code constructions, and applications

YM Chee, T Etzion, HM Kiah… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
The de Bruijn graph, its sequences, and their various generalizations, have found many
applications in information theory, including many new ones in the last decade. In this paper …

Correcting non-binary burst deletions/insertions with de Bruijn symbol-maximum distance separable codes

C Yi, J Zhou, Y Li, Z An, Y Li… - IEEE Communications …, 2023 - ieeexplore.ieee.org
We propose a deterministic decoding scheme to correct a block of deletions/insertions of
length up to with a high probability for the de Bruijn symbol-maximum distance separable …

Correcting multiple deletions and insertions in racetrack memory

J Sima, J Bruck - IEEE Transactions on Information Theory, 2023 - ieeexplore.ieee.org
Racetrack memory is a tape-like structure where data is stored sequentially as a track of
single-bit memory cells. The cells are accessed through read/write ports, called heads …

Correcting deletions in multiple-heads racetrack memories

J Sima, J Bruck - 2019 IEEE international symposium on …, 2019 - ieeexplore.ieee.org
One of the main challenges in developing racetrack memory systems is the limited precision
in controlling the track shifts, that in turn affects the reliability of reading and writing the data …

Binary Codes for Correcting Asymmetric Adjacent Transpositions and Deletions

S Wang, VYF Tan - IEEE Transactions on Communications, 2024 - ieeexplore.ieee.org
Codes in the Damerau–Levenshtein metric have received some attention by the research
community recently owing to their applications in DNA-based data storage. In particular …

Error-Correcting Codes with Large Field Size under Non-Binary Segmented Burst Deletion/Insertion Channels and Unknown Codeword Boundaries

C Yi, L Zou, Y Li, Z Qiu, Y Hu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
In this paper, we construct non-binary codes of length N which correct errors under a non-
binary segment-N maxburst-D deletion and maxburst-S insertion (NB-SBDI (N, D, S)) …

Coding for transverse-reads in domain wall memories

YM Chee, A Vardy, E Yaakobi - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
Transverse-read is a novel technique to detect the number of '1's stored in domain wall
memory, also known as racetrack memory, without shifting any domains. Motivated by this …