Power dissipation during scan testing is becoming an important concern as design sizes
and gate densities increase. While several approaches have been recently proposed for …

A highly parallel (more than a thousand) dataflow machine EM-4 is now under development.
The EM-4 design principle is to construct a high performance computer using a compact …

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in
the deep submicron era. However, its applicability is being severely challenged since …

This paper presents a novel low-transition linear feedback shift register (LFSR) that is based
on some new observations about the output sequence of a conventional LFSR. The …

This paper presents a new and comprehensive low-power test scheme compatible with a
test compression environment. The key contribution of this paper is a flexible test-application …

High power dissipation can occur when the response to a test vector is captured by flip-flops
in scan testing, resulting in excessive JR drop, which may cause significant capture-induced …

High-quality at-speed scan testing, characterized by high small-delay-defect detecting
capability, is indispensable to achieve high delay test quality for DSM circuits. However …

This paper presents a procedure for inserting test points at the outputs of scan elements of a
full-scan circuit in such a manner that the peak power during scan testing is kept below a …

The embedded deterministic test-based compression uses cube merging to reduce a pattern
count, the amount of test data, and test time. It gradually expands a test pattern by …

This paper presents a new and comprehensive power-aware test scheme compatible with a
test compression environment. The key contribution of the paper is a flexible test application …