Most parallel SystemC approaches have two limitations:(a) the user must manually separate
all parallel threads to avoid data corruption due to race conditions, and (b) available …

For effective embedded system design, transaction level modeling (TLM) must explicitly
expose any available parallelism in the application. Traditional TLM in SystemC utilizes …

The emergence of data-intensive applications, such as Deep Neural Networks (DNNs),
exacerbates the well-known memory bottleneck in computer systems and demands early …

Many parallel SystemC approaches expect a thread safe and conflict free model from the
designer. Alternatively, an advanced compiler can identify and avoid possible parallel …

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market
constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while …

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market
constraints, Virtual Prototyping (VP) tools based on SystemC/TLM2. 0 must get faster while …

Transaction level models of systems-on-chip in SystemC are commonly used in the industry
to provide an early simulation environment. The SystemC standard imposes coroutine …

The paper presents a solution for hierarchical simulation of onboard networks, which allows
performing simulation at different levels of details. This solution was integrated into a new …

The IEEE standard SystemC language [13] is widely used for the specification, modeling,
validation, and evaluation of electronic system level (ESL) models. The Accellera Systems …

Embedded systems are often used in safety-critical applications like cars or airplanes. This
makes it crucial to verify their hardware and software under all circumstances. In previous …