[HTML][HTML] A review on the fabrication and reliability of three-dimensional integration technologies for microelectronic packaging: Through-Si-via and solder bumping …

DH Cho, SM Seo, JB Kim, SH Rajendran, JP Jung - Metals, 2021 - mdpi.com
With the continuous miniaturization of electronic devices and the upcoming new
technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation …

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

YJ Jang, A Sharma, JP Jung - Materials, 2023 - mdpi.com
Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …

Electrochemical spectroscopic analysis of additives in copper plating baths by DRT and multivariate approach

M Verrucchi, A Comparini, M Bonechi, I del Pace… - Journal of …, 2024 - Elsevier
The concentration of additives of a copper electroplating bath with a complex matrix are
quantified using electrochemical impedance spectroscopy (EIS). The Experimental data …

Synergistic effects of additives on impurity residues in high-speed copper electrodeposition and voiding propensity in solder joints

KL Tsai, CM Chen, CE Ho - Journal of the Taiwan Institute of Chemical …, 2024 - Elsevier
Background Copper electroplating is an important technology used to construct the
interconnects/conductors in microelectronic industry. Functional additives such as …

Electroplated functional materials with 3D nanostructures defined by advanced optical lithography and their emerging applications

J Ahn, S Hong, YS Shim, J Park - Applied Sciences, 2020 - mdpi.com
Electroplating has been favored to date as a surface treatment technology in various
industries in the development of semiconductors, automobiles, ships, and steel due to its …

TXV Technology: The cornerstone of 3D system-in-packaging

HR Zhao, MX Chen, Y Peng, Q Wang, M Kang… - Science China …, 2022 - Springer
Abstract System-in-packaging (SiP) can realize the integration and miniaturization of
electronic devices and it is significant to continue Moore's law. Through-X-via (TXV) …

A State‐of‐the‐Art Review of Through‐Silicon Vias: Filling Materials, Filling Processes, Performance, and Integration

Q Xia, X Zhang, B Ma, K Tao, H Zhang… - Advanced …, 2025 - Wiley Online Library
Through‐silicon via (TSV) technology realizes high‐density interconnections within and
between different dies (chips) by vertically drilling holes in silicon and filling them with …

Preparation and characterization of high thermal conductivity and low CTE polyimide composite reinforced with diamond nanoparticles/SiC whiskers for 3D IC …

J Luo, Y Wu, Y Sun, G Wang, Y Liu, X Zhao, G Ding - Applied Sciences, 2019 - mdpi.com
Low thermal conductivity and large coefficient of thermal expansion (CTE) are the most
serious disadvantages of the polymer dielectric for the interposer redistribution layer (RDL) …

Electrodeposition of Ru on Nanoscale Trench Patterns

Y Kim, J Lee, J Seo, H Han, I Hwang… - ECS Journal of Solid …, 2024 - iopscience.iop.org
Ru deposition in advanced technology nodes can improve performance by providing low
resistance in nanoscale features. In this study, we reported the electrochemical reactions of …

Communication—fast bottom-up filling of high aspect ratio micro vias using a single CTAB additive

H Wu, Z Li, Y Wang, W Zhu - Journal of The Electrochemical …, 2020 - iopscience.iop.org
In this study, by adding a single additive of Cetyltrimethyl Ammonium Bromide (CTAB) to the
electrolyte, the bottom-up filling of micro via (Φ20 μm× 200 μm) was obtained with a fast …