Packetization and routing analysis of on-chip multiprocessor networks
Some current and most future systems-on-chips use and will use network
architectures/protocols to implement on-chip communication. On-chip networks borrow …
architectures/protocols to implement on-chip communication. On-chip networks borrow …
Functional level power analysis: An efficient approach for modeling the power consumption of complex processors
J Laurent, N Julien, E Senn… - … Design, Automation and …, 2004 - ieeexplore.ieee.org
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are
presented. The estimation methodology uses a functional modeling of the processor …
presented. The estimation methodology uses a functional modeling of the processor …
[图书][B] UML for SoC design
G Martin, W Müller - 2006 - books.google.com
A tutorial approach to using the UML modeling language in system-on-chip design Based
on the DAC 2004 tutorial, applicable for students and professionals Contributions by top …
on the DAC 2004 tutorial, applicable for students and professionals Contributions by top …
An instruction-level energy model for embedded VLIW architectures
M Sami, D Sciuto, C Silvano… - IEEE Transactions on …, 2002 - ieeexplore.ieee.org
In this paper, an instruction-level energy model is proposed for the data-path of very long
instruction word (VLIW) pipelined processors that can be used to provide accurate power …
instruction word (VLIW) pipelined processors that can be used to provide accurate power …
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation
J Huang, M Momenzadeh, MB Tahoori… - Proceedings of the 14th …, 2004 - dl.acm.org
Quantum-dot Cellular Automata (QCA) offers a new computing paradigm in nanotechnology.
The basic logic elements of this technology are the inverter and the majority voter. In this …
The basic logic elements of this technology are the inverter and the majority voter. In this …
Hypercube network fault tolerance: A probabilistic approach
Extensive experiments and experience have shown that the well-known hypercube
networks are highly fault tolerant. What is frustrating is that it seems very difficult to properly …
networks are highly fault tolerant. What is frustrating is that it seems very difficult to properly …
SoftExplorer: Estimating and optimizing the power and energy consumption of a C program for DSP applications
E Senn, J Laurent, N Julien, E Martin - EURASIP Journal on Advances in …, 2005 - Springer
We present a method to estimate the power and energy consumption of an algorithm directly
from the C program. Three models are involved: a model for the targeted processor (the …
from the C program. Three models are involved: a model for the targeted processor (the …
Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors
Single chip heterogeneous multiprocessors (SCHMs) are becoming more commonplace,
especially in portable devices where reduced energy consumption is a priority. The use of …
especially in portable devices where reduced energy consumption is a priority. The use of …
Power modeling for heterogeneous processors
As power becomes an ever more important design consideration, there is a need for
accurate power models at all stages of the design process. While power models are …
accurate power models at all stages of the design process. While power models are …
Compiler based exploration of DSP energy savings by SIMD operations
M Lorenz, P Marwedel, T Drager… - ASP-DAC 2004: Asia …, 2004 - ieeexplore.ieee.org
The growing use of digital signal processors (DSPs) in embedded systems necessitates the
use of optimizing compilers supporting their special architecture features. Beside the …
use of optimizing compilers supporting their special architecture features. Beside the …