An automated SEU fault-injection method and tool for HDL-based designs

W Mansour, R Velazco - IEEE Transactions on Nuclear Science, 2013 - ieeexplore.ieee.org
Evaluating the sensitivity to soft-errors of integrated circuits and systems became a main
issue especially if they are intended to operate in space or at high altitudes. In this paper, a …

EC-CFI: Control-Flow Integrity via Code Encryption Counteracting Fault Attacks

P Nasahl, S Sultana, H Liljestrand… - … Security and Trust …, 2023 - ieeexplore.ieee.org
Fault attacks enable adversaries to manipulate the controlflow of security-critical
applications. By inducing targeted faults into the CPU, the software's call graph can be …

SCFIT: A FPGA-based fault injection technique for SEU fault model

A Mohammadi, M Ebrahimi, A Ejlali… - … Design, Automation & …, 2012 - ieeexplore.ieee.org
In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection
technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU …

SEU fault-injection in VHDL-based processors: A case study

W Mansour, R Velazco - Journal of Electronic Testing, 2013 - Springer
Evaluating the sensibility of a given circuit with respect to soft errors became a main issue
especially if it is intended to operate in space or at high altitudes. A hardware/software …

Compositional neural-network modeling of complex analog circuits

RM Hasani, D Haerle, CF Baumgartner… - … Joint Conference on …, 2017 - ieeexplore.ieee.org
We introduce CompNN, a compositional method for the construction of a neural-network
(NN) capturing the dynamic behavior of a complex analog multiple-input multiple-output …

A method and an automated tool to perform SET fault-injection on HDL-based designs

W Mansour, R Velazco, R Ayoubi… - 2013 25th …, 2013 - ieeexplore.ieee.org
A fully automated fault-injection method is presented. It deals with transient faults resulting
from the impact of energetic particles and it can be applied early at design phase, on any …

Fast FPGA-based fault injection tool for embedded processors

MS Shirazi, B Morris, H Selvaraj - International Symposium on …, 2013 - ieeexplore.ieee.org
FPGA-based fault injection methods have recently become more popular since they provide
high speed in fault injection experiments. During each fault injection experiment, FPGA …

Fault-tolerant strategy for real-time system based on evolvable hardware

J Wang, J Liu - Journal of Circuits, Systems and Computers, 2017 - World Scientific
The evolvable hardware (EHW) is widely used in the design of fault-tolerant system. Fault-
tolerant system is really a real-time system, and the recovery time is necessary in fault …

ATPG method with a hybrid compaction technique for combinational digital systems

AR Khatri, A Hayek, J Börcsök - 2016 SAI computing …, 2016 - ieeexplore.ieee.org
In this paper, the Test Pattern Generation (TPG) with a new simple hybrid (dynamic and
static) compaction technique for combinational logic circuits and systems is presented …

[PDF][PDF] 一种基于FPGA 的微处理器软错误敏感性分析方法

梁华国, 孙红云, 孙骏, 黄正峰, 徐秀敏, 易茂祥… - 电子与信息学报, 2017 - edit.jeit.ac.cn
为了自动快速地分析微处理器对软错误的敏感性, 该文提出一种基于FPGA
故障注入的软错误敏感性分析方法. 在FPGA 芯片上同时运行有故障和无故障的两个微处理器 …