First-last: a cost-effective adaptive routing solution for TSV-based three-dimensional networks-on-chip

A Charif, A Coelho, M Ebrahimi… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
3D integration opens up new opportunities for future multiprocessor chips by enabling fast
and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce …

FL-RuNS: A high-performance and runtime reconfigurable fault-tolerant routing scheme for partially connected three-dimensional networks on chip

A Coelho, A Charif, NE Zergainoh… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Three-dimensional networks on chip (3D-NoCs) have been proposed as an enormously
scalable solution to address communication problems in modern systems on chip. Through …

Rout3d: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3d-nocs

A Charif, NE Zergainoh, A Coelho… - 2017 22nd IEEE …, 2017 - ieeexplore.ieee.org
3D integration opens up new opportunities for future multiprocessor chips by enabling fast
and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce …

Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically–Partially Connected 3D-NoC

AA da Silva, L Nogueira, A Coelho… - … Transactions on Very …, 2024 - ieeexplore.ieee.org
Multiprocessor systems-on-chip (MPSoCs) based on 3-D networks-on-chip (3D-NoCs) are
crucial architectures for robust parallel computing, efficiently sharing resources across …

Reflect3d: An Adaptive and Fault-Tolerant Routing Algorithm for Vertically-Partially-Connected 3D-NoC

AA Da Silva, LMES Junior, A Coelho… - 2021 34th SBC …, 2021 - ieeexplore.ieee.org
The combined benefits of the Three-Dimensional (3D) and Network-on-Chip (NoC) schemes
enable designing a high-performance system in a limited chip area. The 3D-NoC major …

Thermal management in 3d networks-on-chip using dynamic link sharing

M Keramati, M Modarressi, SHS Rezaei - Microprocessors and …, 2017 - Elsevier
Abstract 3D integration is a practical solution for overcoming the problems of long and slow
global wires in current and future generations of integrated circuits. This emerging …

A runtime fault-tolerant routing scheme for partially connected 3d networks-on-chip

A Coelho, A Charif, NE Zergainoh… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Three-dimensional Networks-on-Chip (3D-NoC) have emerged as an effective solution to
the scalability and latency issues in modern complex System-On-Chips. Through-Silicon Via …

A Comparative Analysis of Fault Tolerance Methods in 3D-NoC

K Somraj, KK Kumar, BNK Reddy - 2021 Sixth International …, 2021 - ieeexplore.ieee.org
Networks-on-Chips (NoCs) have found wide acceptance in many-core systems for on-chip
communication due to their ease in addressing communication problems in integrated …

Fault Tolerance and Reliability for Partially Connected 3D Networks-on-Chip

AA da Penha Coelho - 2019 - theses.hal.science
Networks-on-Chip (NoC) have emerged as a viable solution for the communication
challenges in highly complex Systems-on-Chip (SoC). The NoC architecture paradigm …

Design, Parallel Simulation and Implementation of High-Performance Fault-Tolerant Network-on-Chip Architectures

MEA Charif - 2017 - theses.hal.science
Networks-on-Chip (NoCs) have proven to be a fast and scalable replacement for buses in
current and emerging many-core systems. They are today an actively researched topic and …