This paper describes both a near term and a long term optical interconnect solution, the first
based on a packaging architecture and the second based on a monolithic photonic CMOS …

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip
communications over high-loss electrical channels such as backplanes. The equalization …

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip
applications. The transceiver employs a number of features for reducing power …

A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is
presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 …

A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is
reported. Based on expected channel characteristics, the proposed I/O features low …

The bandwidth requirement of wireline communications has increased exponentially
because of the ever-increasing demand for data centers and high-performance computing …

Interconnect architectures which leverage high-bandwidth optical channels offer a promising
solution to address the increasing chip-to-chip I/O bandwidth demands. This paper …

A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate
topology with purely digital blocks to substantially reduce power consumption. The receiver …

This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward
equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the …

This study provides a comprehensive review of decision feedback equalisation (DFE) for
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …