With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

This paper introduces GRANNITE, a GPU-accelerated novel graph neural network (GNN)
model for fast, accurate, and transferable vector-based average power estimation. During …

As Moore's law has provided an exponential increase in chip transistor density, the unique
features we can now include in large chips are no longer predominantly limited by area …

Accurate power modeling is crucial for energy-efficient CPU design and runtime
management. An ideal power modeling framework needs to be accurate yet fast, achieve …

The number of transistors that can fit on one monolithic chip has reached billions to tens of
billions in this decade thanks to Moore's Law. With the advancement of every technology …

Power consumption constitutes a major challenge for electronics circuits. One possible way
to deal with this issue is to consider it very soon in the design process in order to explore …

Net length is a key proxy metric for optimizing timing and power across various stages of a
standard digital design flow. However, the bulk of net length information is not available until …

IR drop constraint is a fundamental requirement enforced in almost all chip designs.
However, its evaluation takes a long time, and mitigation techniques for fixing violations may …

In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where
designers define precise design behavior with hardware description languages (HDLs) like …