Fine-grained aging-induced delay prediction based on the monitoring of run-time stress

A Vijayan, A Koneru, S Kiamehr… - … on Computer-Aided …, 2016 - ieeexplore.ieee.org
Run-time solutions based on online monitoring and adaptation are required for resilience in
nanoscale integrated circuits, as design-time solutions and guard bands are no longer …

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods

N Khoshavi, RA Ashraf, RF DeMara, S Kiamehr… - Integration, 2017 - Elsevier
The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …

Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications

F Nakhaee, M Kamal, A Afzali-Kusha, M Pedram… - Integration, 2018 - Elsevier
In this paper, we present an accuracy-aware operating voltage management unit to improve
the lifetime of processors by considering the error-resilient nature of some applications. This …

NBTI and HCI aging prediction and reliability screening during production test

L Yu, J Ren, X Lu, X Wang - IEEE Transactions on Computer …, 2019 - ieeexplore.ieee.org
With the semiconductor manufacturing technology approaching to 14 nm and below, the
reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging …

Device aging: A reliability and security concern

D Kraak, M Taouil, S Hamdioui, P Weckx… - 2018 IEEE 23rd …, 2018 - ieeexplore.ieee.org
Device aging is an important concern in nanoscale designs. Due to aging the electrical
behavior of transistors embedded in an integrated circuit deviates from original intended …

LSTM-based analysis of temporally-and spatially-correlated signatures for intermittent fault detection

X Wang, L Jiang, K Chakrabarty - 2020 IEEE 38th VLSI Test …, 2020 - ieeexplore.ieee.org
Intermittent faults are a critical reliability threat in deep submicron VLSI circuits. These faults
occur non-deterministically due to unstable hardware and unpredictable operating …

Prognosis of NBTI aging using a machine learning scheme

N Karimi, K Huang - … Symposium on Defect and Fault Tolerance …, 2016 - ieeexplore.ieee.org
Circuit aging is an important failure mechanism in nanoscale designs and is a growing
concern for the reliability of future systems. Aging results in circuit performance degradation …

Workload-aware worst path analysis of processor-scale NBTI degradation

S Bian, M Shintani, S Morita, H Awano… - Proceedings of the 26th …, 2016 - dl.acm.org
As technology further scales semiconductor devices, aging-induced device degradation has
become one of the major threats to device reliability. In addition, aging mechanisms like the …

A survey of aging monitors and reconfiguration techniques

LR Juracy, MT Moreira, AM Amory… - arXiv preprint arXiv …, 2020 - arxiv.org
CMOS technology scaling makes aging effects an important concern for the design and
fabrication of integrated circuits. Aging deterioration reduces the useful life of a circuit …

Instruction-level NBTI stress estimation and its application in runtime aging prediction for embedded processors

I Moghaddasi, A Fouman, ME Salehi… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Lifetime reliability management of miniaturized CMOS devices continuously gets more
importance with the shrinking of technology size. Neither of existing design-time solutions …