Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
[HTML][HTML] Edge computing: A survey on the hardware requirements in the internet of things world
In today's world, ruled by a great amount of data and mobile devices, cloud-based systems
are spreading all over. Such phenomenon increases the number of connected devices …
are spreading all over. Such phenomenon increases the number of connected devices …
An energy-efficient comparator with dynamic floating inverter amplifier
This article presents an energy-efficient comparator design. The pre-amplifier adopts an
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …
A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier
This article presents a second-order noise-shaping (NS) successive approximation register
(SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT) …
(SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT) …
A low power 12-bit 1-kS/s SAR ADC for biomedical signal processing
In this paper, a 12-bit 1-kS/s successive approximation register analog-to-digital converter
(ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to …
(ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to …
A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC with opamp-less time-domain integrator
SE Hsieh, CC Hsieh - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This paper presents a 13-bit high-resolution two-step analog-to-digital converter (ADC).
Successive approximation register (SAR)-ADCs and an incremental sigma-delta modulator …
Successive approximation register (SAR)-ADCs and an incremental sigma-delta modulator …
An energy-efficient time-domain incremental zoom capacitance-to-digital converter
This article presents an incremental two-step capacitance-to-digital converter (CDC) with a
time-domain ΔΣ modulator (TDΔΣM). Unlike the classic two-step CDCs, this work replaces …
time-domain ΔΣ modulator (TDΔΣM). Unlike the classic two-step CDCs, this work replaces …
A 0.5-V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization
SE Hsieh, CC Kao, CC Hsieh - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
This paper presents a 0.5-V 12-bit low-voltage power-efficient successive-approximation
register (SAR) analogto-digital converter (ADC) using an adaptive time-domain (ATD) …
register (SAR) analogto-digital converter (ADC) using an adaptive time-domain (ATD) …
Low-power SAR ADCs: Basic techniques and trends
P Harpe - IEEE Open Journal of the Solid-State Circuits Society, 2022 - ieeexplore.ieee.org
With the advent of small, battery-powered devices, power efficiency has become of
paramount importance. For analog-to-digital converters (ADCs), the successive …
paramount importance. For analog-to-digital converters (ADCs), the successive …
A 10-bit 120-MS/s SAR ADC with reference ripple cancellation technique
This article presents a reference ripple cancellation technique for high-speed successive
approximation register analog-to-digital converters (SAR ADCs) to address the reference …
approximation register analog-to-digital converters (SAR ADCs) to address the reference …