BACKGROUND In an effort to deal with and simplify otherwise extremely complex design
rules at advanced process rules, foundries are now turning to a different approach in which …

Disclosed are techniques for implementing DRC clean multi-patterning process nodes with
lateral fills. These techniques identify design rules governing multi-patterning and track …

A computer implemented method for decomposing a layout of a portion of an integrated
circuit is presented. The layout includes a first multitude of polygons. The method includes …

According to one embodiment of the present invention, a computer-implemented method for
validating a design includes generating, using the computer, a first graph representative of …

US9652579B1 - Methods, systems, and computer program product for implementing DRC
clean multi-patterning process nodes with parallel fills in electronic designs - Google …

US9659138B1 - Methods, systems, and computer program product for a bottom-up electronic
design implementation flow and track pattern definition for multiple-patterning lithographic …

Aspects of the disclosed techniques relate to techniques of layout decomposition for multiple
patterning lithography. Data of a coloring graph are derived from layout data for a layout …

US9652581B2 - Directed self-assembly-aware layout decomposition for multiple patterning -
Google Patents US9652581B2 - Directed self-assembly-aware layout decomposition for …

BACKGROUND In an effort to deal with and simplify otherwise extremely complex design
rules at advanced process rules, foundries are now turning to a different approach in which …

(57) ABSTRACT A multiple patterning decomposition method for IC is pro vided. Features of
layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a …