Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip

A Eghbal, PM Yaghini, N Bagherzadeh… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Reliability is one of the most challenging problems in the context of three-dimensional
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …

Towards efficient on-chip communication: A survey on silicon nanophotonics and optical networks-on-chip

UU Nisa, J Bashir - Journal of Systems Architecture, 2024 - Elsevier
Silicon nanophotonics, with its high-speed, low-loss optical interconnects, and high
computation capabilities, is seen as one of the promising technologies that can easily …

An enhancement of crosstalk avoidance code based on fibonacci numeral system for through silicon vias

X Cui, X Cui, Y Ni, M Miao… - IEEE Transactions on Very …, 2017 - ieeexplore.ieee.org
Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-
D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk …

3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs

Z Shirmohammadi, HZ Sabzi… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional
integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and …

Capacitive and inductive tsv-to-tsv resilient approaches for 3d ics

PM Yaghini, A Eghbal, SS Yazdi… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-
dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in …

Coupling mitigation in 3-D multiple-stacked devices

PM Yaghini, A Eghbal, M Khayambashi… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
A 3-D multiple-stacked IC has been proposed to support energy efficiency for data center
operations as dynamic RAM (DRAM) scaling improves annually. 3-D multiple-stacked IC is a …

Capacitive coupling mitigation for TSV-based 3D ICs

A Eghbal, PM Yaghini… - 2015 IEEE 33rd VLSI …, 2015 - ieeexplore.ieee.org
TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the
circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a …

Accurate system-level TSV-to-TSV capacitive coupling fault model for 3D-NoC

PM Yaghini, A Eghbal, SS Yazdi… - Proceedings of the 9th …, 2015 - dl.acm.org
TSV-based 3D-NoC has been introduced as a viable solution for integrating more cores on
a chip, while imposing smaller footprint area and better timing performance as compared to …

3D-DPS: An efficient 3D-CAC for reliable data transfer in 3D ICs

Z Shirmohammadi, N Rohbani… - 2016 12th European …, 2016 - ieeexplore.ieee.org
Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability,
higher throughput, and lower power consumption with respect to Two Dimensional …

[图书][B] Reliability enhancement of many-core processors

M SeyyedHosseini - 2017 - search.proquest.com
Many-core systems are of great importance for building the exascale computing machine
targeted for 2020. Last-Level Cache (LLC), as the largest on-chip shared memory in many …