Semiconductor memory is a crucial part of today's electronic systems. The percentage of
silicon areas devoted to memory components in embedded systems and systems-on-chip …

The main memory in today's systems is based on DRAMs, which may offer low cost and high
density storage for large amounts of data but it comes with a main drawback; DRAM cells …

This paper addresses the problem of describing the complex linked coupling faults of
memory devices and formulating the necessary and sufficient conditions for their detection …

A memory fault model regarding the unlinked static three-cell coupling faults in n× 1 random-
access memories is discussed. This model is an extension of the well-known model of …

This paper presents the universal address sequence generator (UASG) for memory built-in-
self-test. The studies are based on the proposed universal method for generating address …

Conventional march memory tests have high fault coverage, especially for simple faults like
stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard …

Studying the efficiency of memory system tests, we have to take into consideration the
complexity of generating all 2 k combinations for k memory cells, which is an essential and …

Conventional memory tests based on only one run have constant and low faults coverage
especially for Pattern Sensitive Faults (PSF). To increase faults coverage the multiple run …

This chapter presents UniServer that exploits the increased variability within CPUs and
memories manufactured in advanced nanometer nodes that give rise to another type of …

The rapid increase of processed data is driving the aggressive scaling of DRAM for meeting
the needs of higher memory density and bandwidth. As a result of the high memory demand …