[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
Embedded deterministic test
J Rajski, J Tyszer, M Kassab… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
This paper presents a novel test-data volume-compression methodology called the
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Embedded deterministic test for low cost manufacturing test
J Rajski, J Tyszer, M Kassab… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper introduces embedded deterministic test (EDT) technology, which reduces
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …
Reducing test data volume using LFSR reseeding with seed compression
CV Krishna, NA Touba - Proceedings. International Test …, 2002 - ieeexplore.ieee.org
A new lossless test vector compression scheme is presented which combines linear
feedback shift register (LFSR) reseeding and statistical coding in a powerful way. Test …
feedback shift register (LFSR) reseeding and statistical coding in a powerful way. Test …
Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
D Xiang, X Wen, LT Wang - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on
weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture …
weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture …
Checking equivalence of quantum circuits and states
GF Viamontes, IL Markov… - 2007 IEEE/ACM …, 2007 - ieeexplore.ieee.org
Among the post-CMOS technologies currently under investigation, quantum computing (QC)
holds a special place. QC offers not only extremely small size and low power, but also …
holds a special place. QC offers not only extremely small size and low power, but also …
Weighted pseudorandom hybrid BIST
A Jas, CV Krishna, NA Touba - IEEE Transactions on Very …, 2004 - ieeexplore.ieee.org
This paper presents a new test data-compression scheme that is a hybrid approach between
external testing and built-in self-test (BIST). The proposed approach is based on weighted …
external testing and built-in self-test (BIST). The proposed approach is based on weighted …
Test set embedding for deterministic BIST using a reconfigurable interconnection network
L Li, K Chakrabarty - … Transactions on computer-aided design of …, 2004 - ieeexplore.ieee.org
We present a new approach for deterministic built-in self-test (BIST) in which a
reconfigurable interconnection network (RIN) is placed between the outputs of a …
reconfigurable interconnection network (RIN) is placed between the outputs of a …
Low-power programmable PRPG with test compression capabilities
M Filipek, G Mrugalski, N Mukherjee… - … Transactions on Very …, 2014 - ieeexplore.ieee.org
This paper describes a low-power (LP) programmable generator capable of producing
pseudorandom test patterns with desired toggling levels and enhanced fault coverage …
pseudorandom test patterns with desired toggling levels and enhanced fault coverage …