Applying deep learning to the cache replacement problem
Despite its success in many areas, deep learning is a poor fit for use in hardware predictors
because these models are impractically large and slow, but this paper shows how we can …
because these models are impractically large and slow, but this paper shows how we can …
[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
SHiP: Signature-based hit predictor for high performance caching
The shared last-level caches in CMPs play an important role in improving application
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …
Bounded geometries, fractals, and low-distortion embeddings
The doubling constant of a metric space (X, d) is the smallest value/spl lambda/such that
every ball in X can be covered by/spl lambda/balls of half the radius. The doubling …
every ball in X can be covered by/spl lambda/balls of half the radius. The doubling …
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
Large last-level caches (L 3 Cs) are frequently used to bridge the performance and power
gap between processor and memory. Although traditional processors implement caches as …
gap between processor and memory. Although traditional processors implement caches as …
PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches
Y Xie, GH Loh - ACM SIGARCH Computer Architecture News, 2009 - dl.acm.org
Many multi-core processors employ a large last-level cache (LLC) shared among the
multiple cores. Past research has demonstrated that sharing-oblivious cache management …
multiple cores. Past research has demonstrated that sharing-oblivious cache management …
Sampling dead block prediction for last-level caches
Last-level caches (LLCs) are large structures with significant power requirements. They can
be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of …
be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of …
Perceptron learning for reuse prediction
The disparity between last-level cache and memory latencies motivates the search for
efficient cache management policies. Recent work in predicting reuse of cache blocks …
efficient cache management policies. Recent work in predicting reuse of cache blocks …
Counter-based cache replacement and bypassing algorithms
M Kharbutli, Y Solihin - IEEE Transactions on Computers, 2008 - ieeexplore.ieee.org
Recent studies have shown that, in highly associative caches, the performance gap between
the least recently used (LRU) and the theoretical optimal replacement algorithms is large …
the least recently used (LRU) and the theoretical optimal replacement algorithms is large …
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Data caches in general-purpose microprocessors often contain mostly dead blocks and are
thus used inefficiently. To improve cache efficiency, dead blocks should be identified and …
thus used inefficiently. To improve cache efficiency, dead blocks should be identified and …