Variability-driven module selection with joint design time optimization and post-silicon tuning
F Wang, X Wu, Y Xie - 2008 Asia and South Pacific Design …, 2008 - ieeexplore.ieee.org
Increasing delay and power variation are significant challenges to the designers as
technology scales to the deep sub-micron (DSM) regime. Traditional module selection …
technology scales to the deep sub-micron (DSM) regime. Traditional module selection …
FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization
While technology scaling has presented many new and exciting opportunities, new design
challenges have arisen due to increased density, and delay and power variations. High …
challenges have arisen due to increased density, and delay and power variations. High …
Timing variation-aware task scheduling and binding for MPSoC
HN Chon, T Kim - 2009 Asia and South Pacific Design …, 2009 - ieeexplore.ieee.org
This work addresses the new problem of timing variation-aware task scheduling and binding
(TSB) for multiprocessor system-on-chip (MPSoC) architecture in the system-level design …
(TSB) for multiprocessor system-on-chip (MPSoC) architecture in the system-level design …
A variation aware high level synthesis framework
The worst-case delay/power of function units has been used in traditional high level
synthesis to facilitate design space exploration. As technology scales to nanometer regime …
synthesis to facilitate design space exploration. As technology scales to nanometer regime …
Process variation aware system-level task allocation using stochastic ordering of delay distributions
L Singhal, E Bozorgzadeh - 2008 IEEE/ACM International …, 2008 - ieeexplore.ieee.org
Design variability due to within-die and die-to-die variations has potential to significantly
reduce the maximum operating frequency and effective performance of the system in future …
reduce the maximum operating frequency and effective performance of the system in future …
Tolerating process variations in high-level synthesis using transparent latches
Considering process variability at the behavior synthesis level is necessary, because it
makes some instances of function units slower and others faster, resulting in unbalanced …
makes some instances of function units slower and others faster, resulting in unbalanced …
A distributed clustered architecture to tackle delay variations in datapath synthesis
AA Del Barrio, J Cong… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Due to the necessity of handling unexpected events in execution time, eg, to support
process variations, new mechanisms for dealing with every possible behavior of the …
process variations, new mechanisms for dealing with every possible behavior of the …
Statistical high-level synthesis under process variability
Statistical High-Level Synthesis under Process Variability Page 1 Statistical High-Level
Synthesis under Process Variability Yuan Xie and Yibo Chen Pennsylvania State University IT IS …
Synthesis under Process Variability Yuan Xie and Yibo Chen Pennsylvania State University IT IS …
Variability-aware architecture level optimization techniques for robust nanoscale chip design
SP Mohanty, M Gomathisankaran… - Computers & Electrical …, 2014 - Elsevier
The design space for nanoscale CMOS circuits is vast, with multiple dimensions
corresponding to process variability, leakage, power, thermal, reliability, security, and yield …
corresponding to process variability, leakage, power, thermal, reliability, security, and yield …
Timing variation-aware scheduling and resource binding in high-level synthesis
Due to technological scaling, process variations have increased significantly, resulting in
large variations in the delay of the functional units. Hence, the worst-case approach is …
large variations in the delay of the functional units. Hence, the worst-case approach is …