A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches
Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …
increase in the size of on-chip caches. Since SRAM has low density and consumes large …
Spin-transfer torque memories: Devices, circuits, and systems
Spin-transfer torque magnetic memory (STT-MRAM) has gained significant research interest
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …
Shiftsreduce: Minimizing shifts in racetrack memory 4.0
Racetrack memories (RMs) have significantly evolved since their conception in 2008,
making them a serious contender in the field of emerging memory technologies. Despite key …
making them a serious contender in the field of emerging memory technologies. Despite key …
Prediction hybrid cache: An energy-efficient STT-RAM cache architecture
Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density
alternative to SRAM for large on-chip caches. However, its high write energy has been …
alternative to SRAM for large on-chip caches. However, its high write energy has been …
Write intensity prediction for energy-efficient non-volatile caches
This paper presents a novel concept called write intensity prediction for energy-efficient non-
volatile caches as well as the architecture that implements the concept. The key idea is to …
volatile caches as well as the architecture that implements the concept. The key idea is to …
3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems
Multi-level Cell (MLC) Phase Change Memory (PCM) has many attractive features to be
used as main memory for embedded systems. These features include low power, high …
used as main memory for embedded systems. These features include low power, high …
A low-power hybrid magnetic cache architecture exploiting narrow-width values
Modern microprocessors have increased the word width to 64-bits to support larger main
memory sizes. It has been observed that data can often be represented by relatively few bits …
memory sizes. It has been observed that data can often be represented by relatively few bits …
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement
because of its excellent features, such as fast read access, high density, low leakage power …
because of its excellent features, such as fast read access, high density, low leakage power …
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors
The recent emergence of various Non-Volatile Memories (NVMs), with many attractive
characteristics such as low leakage power and high-density, provides us with a new way of …
characteristics such as low leakage power and high-density, provides us with a new way of …
Hybrid nonvolatile disk cache for energy-efficient and high-performance systems
NAND flash memory has been employed as disk cache in recent years. It has the
advantages of high performance, low leakage power, and cost efficiency. However, flash …
advantages of high performance, low leakage power, and cost efficiency. However, flash …