A method and apparatus for including in a processor instructions for performing multiply-add
operations on packed data. In one embodiment, a processor is coupled to a memory. The …

57 ABSTRACT A digital signal decoder system for receiving compressed encoded digitized
video signals and transmitting decom pressed decoded digital video signals includes a FIFO …

A method and apparatus for performing matrix transformations including multiply-add
operations and byte shuffle operations on packed data in a processor. In one embodiment …

[57] ABSTRACT A method and apparatus for including in a processor instruc tions for
performing multiply-subtract operations on packed data. In one embodiment, a processor is …

3,711,692 1/1973 Batcher............................. 364/715.09 Zafm" 3,723,715 3/1973 Chen a a1
364/78604 4,139,899 2/1979'I 'ulpoleetal....... 395/565[57] ABSTRACT 243: 1: gusmngaal …

A method and apparatus for including in a processor instructions for performing multiply-add
operations on packed data. In one embodiment, a processor is coupled to a memory. The …

US7430578B2 - Method and apparatus for performing multiply-add operations on packed byte
data - Google Patents US7430578B2 - Method and apparatus for performing multiply-add …

Zafman 57 ABSTRACT A method for manipulating packed data in a computer System. The
method includes the Steps of decoding a Single Instruction Multiple Data (SIMD) pack …

US6385634B1 - Method for performing multiply-add operations on packed data - Google
Patents US6385634B1 - Method for performing multiply-add operations on packed data …

Zafman 57 ABSTRACT A method and apparatus for executing floating point and packed
data instructions using a Single physical register file that is aliased. According to one aspect …