Write-back invalidate by key identifier
V Shanbhogue, S Van Doren, G Neiger… - US Patent …, 2022 - Google Patents
An integrated circuit includes a core and memory controller coupled to a last level cache
(LLC). A first key identifier for a first program is associated with physical addresses of …
(LLC). A first key identifier for a first program is associated with physical addresses of …
Cached web probes for monitoring user experience
C Zheng, S Devarajan, V Mahajan… - US Patent …, 2023 - Google Patents
H04L63/0428—Network architectures or network communication protocols for network
security for providing a confidential data exchange among entities communicating through …
security for providing a confidential data exchange among entities communicating through …
Page swapping to protect memory devices
S Seyedzadehdelcheh, S Srikanth - US Patent 12,026,387, 2024 - Google Patents
A page swapping memory protection system tracks accesses to physical memory pages,
such as in a table with each row storing a physical memory page address and a counter …
such as in a table with each row storing a physical memory page address and a counter …
Final cache directory state indication
JD Kohl, GW Alexander, T Bronson, AV Giri… - US Patent …, 2024 - Google Patents
A method for managing designated authority status in a cache line includes identifying an
initial designated authority (DA) member cache for a cache line, transferring DA status from …
initial designated authority (DA) member cache for a cache line, transferring DA status from …
Memory row recording for mitigating crosstalk in dynamic random access memory
S Seyedzadehdelcheh - US Patent 11,488,654, 2022 - Google Patents
A method includes adding a set of one or more victim rows to a first probabilistic filter and to
a second probabilistic filter, in response to a memory access request, identifying a candidate …
a second probabilistic filter, in response to a memory access request, identifying a candidate …