A review of failure analysis methods for advanced 3D microelectronic packages

Y Li, PKM Srinath, D Goyal - Journal of Electronic Materials, 2016 - Springer
Advanced three dimensional (3D) packaging is a key enabler in driving form factor
reduction, performance benefits, and package cost reduction, especially in the fast paced …

Four dimensional (4D) microstructural evolution of Cu6Sn5 intermetallic and voids under electromigration in bi-crystal pure Sn solder joints

MB Kelly, S Niverty, N Chawla - Acta Materialia, 2020 - Elsevier
Electromigration (EM) causes intermetallic and void growth that decreases the reliability and
lifetime of solder joints. As a diffusion-controlled process, EM is highly dependent on the …

Electromigration in Bi-crystal pure Sn solder joints: Elucidating the role of grain orientation

MB Kelly, S Niverty, N Chawla - Journal of Alloys and Compounds, 2020 - Elsevier
Intermetallic compound (IMC) and void growth are electromigration (EM) damage
mechanisms that are controlled by the anisotropic diffusion of Cu in β-tetragonal Sn solder …

Solder void size reduction in semiconductor package by vacuum reflow and pressure cure processes

SM Yeo, HK Yow, KH Yeoh - Soldering & Surface Mount Technology, 2022 - emerald.com
Purpose Semiconductor packaging industry has in recent years tightened the tolerance
criteria for acceptable solder void size in the semiconductor packages due to the high usage …

An Accurate and Intelligent Approach to Predicting the Power Device Fatigue Failure Process

Y Liu, L Jia, L Wang, J Wang, J Zhang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
It is significant to study power device package fatigue failure as it seriously affects the
reliability of power systems. Nevertheless, the research of the power device failure process …

Evaluation of lead-free solder bump voiding ball grid array packages using laser ultrasound and interferometric technique

IC Ume, J Gong - IEEE Transactions on Components …, 2013 - ieeexplore.ieee.org
Solder joint voids are usually formed by the entrapped gas bubbles during the reflow
process and are common in all surface mount applications. It is a controversial issue on the …

Critical Threshold Limit for Effective Solder Void Size Reduction by Vacuum Reflow Process for Power Electronics Packaging

SM Yeo, HK Yow, KH Yeoh - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In recent years, power electronics packaging industry has tightened the tolerance criteria for
acceptable solder void size to below 5% in the power packages. Vacuum reflow technology …

High resolution and fast throughput-time x-ray computed tomography for semiconductor packaging applications

Y Li, M Pacheco, D Goyal, JW Elmer… - 2014 IEEE 64th …, 2014 - ieeexplore.ieee.org
The recent applications of 3D X-ray computed tomography (CT) in microelectronic
packages, including nondestructive failure analysis, defect monitoring in solder joints and …

Failure Analysis in Advanced Driver Assistance Systems

Y Li, H Shi - Advanced Driver Assistance Systems and Autonomous …, 2022 - Springer
Failure analysis (FA) could provide timely feedback to process optimization and solution
paths for system failures; thus, it is critical for the development of advanced driver assistance …

Root cause investigation of lead-free solder joint interfacial failures after multiple reflows

Y Li, O Hatch, P Liu, D Goyal - Journal of Electronic Materials, 2017 - Springer
Solder joint interconnects in three-dimensional (3D) packages with package stacking
configurations typically must undergo multiple reflow cycles during the assembly process. In …