Recent trend of FinFET devices and its challenges: A review

RS Pal, S Sharma, S Dasgupta - 2017 Conference on …, 2017 - ieeexplore.ieee.org
Recent technological demand of FinFETs have been explored and reviewed in this work.
The downscaling of the conventional MOSFET urge to the researchers to innovate new …

Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation

NP Maity, R Maity, S Maity, S Baishya - Journal of Computational …, 2019 - Springer
A comparative analysis of the trigate fin-shaped field-effect transistor (FinFET) and quantum
FinFET (QFinFET) is carried out by using density gradient quantization models in the …

Parasitic capacitance model for stacked gate-all-around nanosheet FETs

S Sharma, S Sahay, R Dey - IEEE Transactions on Electron …, 2023 - ieeexplore.ieee.org
Gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) are hailed as the most
promising architecture for the incessant scaling of MOSFETs to the sub-5-nm technology …

A review on the compact modeling of parasitic capacitance: from basic to advanced FETs

SM Sharma, A Singh, S Dasgupta… - Journal of Computational …, 2020 - Springer
This paper presents a review on the development of parasitic-capacitance modeling for
metal–oxide–semiconductor field-effect transistors (MOSFETs), covering models developed …

Charge-Based Trans-Capacitance Model for SiO2/HfO2 Based Nano Scale Trigate FinFET Including Quantum Mechanical Effect

S Panchanan, R Maity, S Baishya, NP Maity - Silicon, 2024 - Springer
A charge based trans-capacitance model is proposed for undoped or lightly doped Trigate
FinFET. The drain current continuity principle and the Ward-Dutton linear charge partition …

Modeling multigate negative capacitance transistors with self-heating effects

Y Jiao, X Huang, Z Rong, Z Ji, R Wang… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
A unified model for multigate negative capacitance transistors with self-heating effects
(SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure …

Parasitic Gate Capacitance Model for N-Stack Forksheet FETs

S Sharma, S Sahay, R Dey - IEEE Transactions on Electron …, 2024 - ieeexplore.ieee.org
The gate-all-around nanosheet (NS) field effect transistors (FETs) are hailed as the most
promising candidate for scaling the CMOS technology beyond the 5-nm technology node …

FinFETs for RF applications: a literature review

SM Sharma, S Dasgupta… - 2018 Conference on …, 2018 - ieeexplore.ieee.org
Recent studies on FinFET pointed out the advantage of immunity from short channel effects
(SCEs) and their performances at high frequencies need attention. In this paper, we review …

Design of quaternary inverter using 32nm SOI technology

D Sagar, SC Sannamani, KSV Patel… - … on Advances in …, 2023 - ieeexplore.ieee.org
In VLSI design due to continuous increase in chip density and decline in size of CMOS
technology node, number of interconnects become one of the major concern. To avoid …

An improved analytical model of outer fringe capacitance of multifin diamond shaped raised source/drain FinFET

SM Sharma, S Dasgupta, MV Kartikeyan - Silicon, 2021 - Springer
Recent studies have pointed out that FinFET are immune to short channel effects (SCEs) but
their performances at high frequencies are compromised due to strong fringing field …