Hardware security has become a hot topic recently with more and more researchers from
related research domains joining this area. However, the understanding of hardware …

Scan chain based attacks are a kind of side channel attack, which targets one of the most
important feature of today's hardware-the test circuitry. Design for Testability (DFT) is a …

With the growing adoption of DevOps and the rise of containerization and Continuous
Integration/Continuous Deployment (CI/CD) in software development life cycle (SDLC) has …

Relying on a recently developed gate-level information assurance scheme, we formally
analyze the security of design-for-test (DFT) scan chains, the industrial standard testing …

Designing secure ICs requires fulfilling many design rules in order to protect access to
secret data. However, these security design requirements may be in opposition to test needs …

Scan based Design for Test (DfT) schemes have been in wide use to increase the testability
of digital circuits. The main objective is to ensure that nodes in the Circuit Under Test (CUT) …

Design for test is an integral part of any VLSI chip. However, for secure systems extra
precautions have to be taken to prevent that the test circuitry could reveal secret information …

Scan test is a powerful and popular test technique because it can control and observe the
internal states of the circuit under test. However, scan path would be used to discover the …

Embedded micro-electro-mechanical technologies and network connectivity allow for the
integration of sensing, identification, and communication capabilities into a variety of smart …

Scan chains, a design for testability feature, are included in most modern-day ICs. But, it
opens a side channel for attacking cryptographic chips. We propose a methodology by …