Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

MM Shulaker, TF Wu, A Pal, L Zhao… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
We demonstrate monolithic 3D integration of logic and memory in arbitrary vertical stacking
order with the ability to use conventional inter-layer vias to connect between any layers of …

Leveraging 3D technologies for hardware security: Opportunities and challenges

P Gu, S Li, D Stow, R Barnes, L Liu, Y Xie… - Proceedings of the 26th …, 2016 - dl.acm.org
3D die stacking and 2.5 D interposer design are promising technologies to improve
integration density, performance and cost. Current approaches face serious issues in …

Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications

Z Wang - Microelectronic Engineering, 2019 - Elsevier
As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …

Monolithic 3D integration: A path from concept to reality

MM Shulaker, TF Wu, MM Sabry, H Wei… - … , Automation & Test …, 2015 - ieeexplore.ieee.org
Monolithic three-dimensional (3D) integration enables revolutionary digital system
architectures of computation immersed in memory. Vertically-stacked layers of logic circuits …

High thermal conductivity insulators for thermal management in 3D integrated circuits

Ç Köroğlu, E Pop - IEEE Electron Device Letters, 2023 - ieeexplore.ieee.org
As physical transistor scaling nears its fundamental limits and many applications are
increasingly bottlenecked by memory bandwidth, three-dimensional (3D) integration is a …

Exploiting carbon nanotube FET and magnetic tunneling junction for near-memory-computing paradigm

N Yang, X Wang, X Lin, W Zhao - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The traditional von Neumann computing architecture based on metal-oxide field-effect-
transistors (MOSFETs) is more and more incompetent for the increasing demand for …

Three dimensional integrated circuit

I Michael - US Patent 9,704,835, 2017 - Google Patents
A method comprises providing a first substrate having dielectric structures and conductive
structures. Ions are implanted into the first substrate, the ions traveling through the dielectric …

Electrothermal characterization and optimization of monolithic 3D complementary FET (CFET)

D Jang, SG Jung, SJ Min, HY Yu - IEEE access, 2021 - ieeexplore.ieee.org
For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic
complementary FET (CFET) in DC operation as well as in AC CMOS operation were …

[HTML][HTML] Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

JH Oh, YS Yu - Micromachines, 2023 - mdpi.com
In this study, the electrical characteristics and electrical coupling effect for monolithic 3-
dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM …

Single-crystal islands (SCI) for monolithic 3-D and back-end-of-line FinFET circuits

YW Liu, HW Hu, PY Hsieh, HT Chung… - … on Electron Devices, 2021 - ieeexplore.ieee.org
A single-crystal islands (SCI) technique using low thermal budget pulse laser process is
proposed and demonstrated to fabricate single-crystal silicon islands over amorphous …