3D die stacking and 2.5 D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in …
Z Wang - Microelectronic Engineering, 2019 - Elsevier
As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …
Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits …
Ç Köroğlu, E Pop - IEEE Electron Device Letters, 2023 - ieeexplore.ieee.org
As physical transistor scaling nears its fundamental limits and many applications are increasingly bottlenecked by memory bandwidth, three-dimensional (3D) integration is a …
N Yang, X Wang, X Lin, W Zhao - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The traditional von Neumann computing architecture based on metal-oxide field-effect- transistors (MOSFETs) is more and more incompetent for the increasing demand for …
I Michael - US Patent 9,704,835, 2017 - Google Patents
A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric …
D Jang, SG Jung, SJ Min, HY Yu - IEEE access, 2021 - ieeexplore.ieee.org
For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were …
In this study, the electrical characteristics and electrical coupling effect for monolithic 3- dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM …
YW Liu, HW Hu, PY Hsieh, HT Chung… - … on Electron Devices, 2021 - ieeexplore.ieee.org
A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous …