As a result of CMOS scaling, radiation-induced Single-Event Effects (SEEs) in electronic
circuits became a critical reliability issue for modern Integrated Circuits (ICs) operating under …

With the exponential increase in the number of transistors under fast-paced technology
progress, the soft error induced reliability issue is becoming even more challenging in …

Because most traditional homogeneous and heterogeneous processors have a fixed design
that limits its runtime adaptability, they are not able to cope with the varying application …

Previous studies proposed several code signatures, with large vector dimensions and time-
consuming profiling processes, to detect phase transitions of the overall processor …

This dissertation proposes a cross-layer framework able to synergistically optimize
resilience and power consumption of processor-based systems. It is composed of three …

Adaptive processors can dynamically change their hardware configuration by tuning several
knobs that optimize a given metric, according to the current application. However, the …

A typical multiprocessor system often needs to support a wide spectrum of applications.
Today, error resilience and low power consumption are two crucial, but non-complementary …

Soft error induced bits upset has received increasing attention in reliable processor design.
To measure the processor reliability, Architectural Vulnerability Factor (AVF) is often …

Performance is no longer the only optimization goal when designing a new processor.
Reducing energy consumption is also mandatory: while most of the embedded devices are …

Processor soft error rates are projected to increase as feature sizes scale down
necessitating the adoption of reliability enhancing schemes, but power and performance …