A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance
This paper demonstrates a signal analysis systemon-chip (SoC) consisting of a general-
purpose RISC-V core with vector extensions and a fixed-function signal-processing …
purpose RISC-V core with vector extensions and a fixed-function signal-processing …
A survey on system-on-a-chip design using chisel hw construction language
M Käyrä, TD Hämäläinen - IECON 2021–47th Annual …, 2021 - ieeexplore.ieee.org
This paper presents a survey of functional programming languages in System-on-a-Chip
(SoC) design. The motivation is improving the design productivity by better source code …
(SoC) design. The motivation is improving the design productivity by better source code …
A real-time, 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET
A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC),
integrating a subsampling analog-to-digital converter (ADC) frontend with a digital …
integrating a subsampling analog-to-digital converter (ADC) frontend with a digital …
Physical Design Implementation and Measurement of Timing Metrics of 32-Bit LEON SPARC Processor Used in Space Applications
S Rangeetha, G Abinaya… - … Conference on Circuit …, 2023 - ieeexplore.ieee.org
There are numerous sequential processes involved in the design sequence of VLSI ICs or
processors. It begins with the high-level synthesis, the functional design, and moves on to …
processors. It begins with the high-level synthesis, the functional design, and moves on to …
A hardware co-design workflow for scientific instruments at the edge
As spatial and temporal resolutions of scientific instruments improve, the explosion in the
volume of data produced is becoming a key challenge. It can be a critical bottleneck for …
volume of data produced is becoming a key challenge. It can be a critical bottleneck for …
A generated multirate signal analysis RISC-V SoC in 16nm FinFET
This paper demonstrates a signal analysis SoC consisting of a general-purpose RISC-V
core with vector extensions and a fixed-function signal-processing accelerator. Both the core …
core with vector extensions and a fixed-function signal-processing accelerator. Both the core …
Designing Self-timed Asynchronous Circuits with Chisel
As an embedded library of the Scala programming language that leverages many features
of object-oriented and functional programming, Chisel is a new generation hardware …
of object-oriented and functional programming, Chisel is a new generation hardware …
A Commercially Available Digital Spectrometer ASIC
G Baranauskas, P Racette… - IEEE Journal of …, 2024 - ieeexplore.ieee.org
This paper presents a commercially available, low-power digital spectrometer Application
Specific Integrated Circuit (ASIC). The ASIC computes 8192 frequency bins across the 4 …
Specific Integrated Circuit (ASIC). The ASIC computes 8192 frequency bins across the 4 …
A real-time, analog/digital co-designed 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET
A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling
ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST …
ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST …
[PDF][PDF] Hammer: A platform for agile physical design
E Wang - Master's thesis, EECS Dept, UC Berkeley, 2018 - eecs.berkeley.edu
2.1 Background After looking at the ENIAC, the state of the art computer in 1945, it would be
difficult to imagine that this monstrous beast could ever fit inside the tip of a pen. ENIAC …
difficult to imagine that this monstrous beast could ever fit inside the tip of a pen. ENIAC …