Integrating embedded memory on CMOS logic using thin film transistors
A semiconductor structure that includes a metal layer in a first interlayer dielectric that is
above a semiconductor device. The semiconductor structure includes an embedded …
above a semiconductor device. The semiconductor structure includes an embedded …
Air gaps and capacitors in dielectric layers
TW LaJoie, AA Sharma, VH Le, CJ Ku… - US Patent App. 16 …, 2020 - Google Patents
Inventors: Travis W. LAJOIE, Forest Grove, OR (US); Abhishek A. SHARMA, Hillsboro, OR
(US); Van H. LE, Portland, OR (US); Chieh-Jen KU, Hillsboro, OR (US); Pei-Hua WANG …
(US); Van H. LE, Portland, OR (US); Chieh-Jen KU, Hillsboro, OR (US); Pei-Hua WANG …
Semiconductor structure with a first lower electrode layer and a second lower electrode layer and method for manufacturing same
D Xiao, L Zhang - US Patent 12,137,550, 2024 - Google Patents
A semiconductor structure and a method for manufacturing same. The semiconductor
structure includes a storage unit, which includes: a first dielectric layer and a metal bit line …
structure includes a storage unit, which includes: a first dielectric layer and a metal bit line …
Semiconductor device, solid-state imaging device and electronic device
H Horikoshi - US Patent App. 17/755,848, 2022 - Google Patents
There is provided a semiconductor device that can minimize deterioration of performance of
a capacitor due to a bonding process. Between a first substrate and a second substrate …
a capacitor due to a bonding process. Between a first substrate and a second substrate …
Semiconductor memory device and method for fabricating the same
MT Ryu, SH Uhm, KS Lee, MS Lee, WS Lee… - US Patent …, 2024 - Google Patents
A semiconductor memory device with improved performance by improving interface
characteristics while reducing a leakage current, and a method for fabricating the same are …
characteristics while reducing a leakage current, and a method for fabricating the same are …
Semiconductor memory device and method of manufacturing semiconductor memory device
S Kobayashi, Y Nakakbuo, Y Nonaka - US Patent App. 17/304,191, 2021 - Google Patents
H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by
three-dimensional arrangements, eg with cells on different height levels with source and …
three-dimensional arrangements, eg with cells on different height levels with source and …
Vertical memory cells
A Lilak, W Rachmady, G Dewey, K Jun, HJ Yoo… - US Patent …, 2023 - Google Patents
2019-09-05 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …