Cache coherence plays a major role in manycore systems. The verification of deadlocks is a
challenge in particular, because deadlock freedom is an emerging property. Formal …

This work presents formal modeling of Network-on-Chip (NoC) considering detailed
functional units of NoC. The intricate modeling of NoC router components like buffer, switch …

Latency is a major issue in the design and validation of a Network-on-Chip (NoC). Various
techniques for establishing latency bounds exist. Formal and mathematical methods, such …

The xMAS language allows the high-level modeling of communication fabrics. For
microarchitectural models expressed in xMAS, it was shown that liveness can be proven …

The language xMAS has been designed by Intel with the purpose of modelling and
verification of hardware. Recently, the language was extended with finite state machines to …

When I, as a kid, was being asked who I wanted to become when I grow up, I was always
answering without any doubt–a researcher (and I must say that it was an unusual answer …

Formal verification (FV) has been a proven methodology to expose deep corner cases,
guarantee high design confidence and generate significant Return on Investments (RoI)[2] …