In this paper, a new design concept that engaged accuracy as a design parameter is
proposed. By introducing accuracy as a design parameter, the bottleneck of conventional …

This paper presents an error compensation method for a modified Booth fixed-width
multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate …

In order to cope up with the functional operation criteria, our work concentrate on the
percentage of indefinite values in the tests performed. A low-power broad side test set is …

In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and
two's-complement parallel multipliers for digital signal processing applications are …

The fixed-width multiplier is attractive to many multimedia and digital signal processing
systems which are desirable to maintain a fixed format and allow a little accuracy loss to …

Truncated multipliers compute the n most-significant bits of the n*n bits product. This paper
focuses on variable-correction truncated multipliers, where some partial-products are …

In this paper, we extend our previous methodology for designing a family of low-error area-
efficient fixed-width two's-complement multipliers that receive two n-bit numbers and …

This brief develops a general methodology for designing a lower-error two's-complement
fixed-width multiplier that receives two n-bit numbers and produces an n-bit product. By …

Digital signal processing algorithms often rely heavily on a large number of multiplications,
which is both time and power consuming. However, there are many practical solutions to …

In this paper, a power-efficient 16 times 16 configurable Booth multiplier (CBM) that supports
single 16-b, single 8-b, or twin parallel 8-b multiplication operations is proposed. To …