A survey on deep learning hardware accelerators for heterogeneous hpc platforms
Recent trends in deep learning (DL) imposed hardware accelerators as the most viable
solution for several classes of high-performance computing (HPC) applications such as …
solution for several classes of high-performance computing (HPC) applications such as …
RAELLA: Reforming the arithmetic for efficient, low-resolution, and low-loss analog PIM: No retraining required!
Processing-In-Memory (PIM) accelerators have the potential to efficiently run Deep Neural
Network (DNN) inference by reducing costly data movement and by using resistive RAM …
Network (DNN) inference by reducing costly data movement and by using resistive RAM …
Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms
There are many real-world applications that require high-performance mobile computing
systems for onboard, real-time processing of gathered data due to latency, reliability …
systems for onboard, real-time processing of gathered data due to latency, reliability …
A 73.53 TOPS/W 14.74 TOPS heterogeneous RRAM in-memory and SRAM near-memory SoC for hybrid frame and event-based target tracking
Vision-based high-speed target-identification and tracking is a critical application in
unmanned aerial vehicles (UAV) with wide military and commercial usage. Traditional frame …
unmanned aerial vehicles (UAV) with wide military and commercial usage. Traditional frame …
A heterogeneous rram in-memory and sram near-memory soc for fused frame and event-based target identification and tracking
Accurate identification of the target and tracking it at high speeds using drone-mounted
cameras and compute hardware finds military and commercial applications. Conventional …
cameras and compute hardware finds military and commercial applications. Conventional …
Adc/dac-free analog acceleration of deep neural networks with frequency transformation
The edge processing of deep neural networks (DNNs) is becoming increasingly important
due to its ability to extract valuable information directly at the data source to minimize latency …
due to its ability to extract valuable information directly at the data source to minimize latency …
A 16.38 TOPS and 4.55 POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation
Edge artificial intelligence applications impose rigorous demands on local hardware to
improve throughput and energy efficiency. Computing-in-memory (CIM) architectures …
improve throughput and energy efficiency. Computing-in-memory (CIM) architectures …
SNPU: Always-on 63.2 μW face recognition spike domain convolutional neural network processor with spike train decomposition and shift-and-accumulation unit
Recently, always-on face recognition (FR) and action recognition chips are widely
developed in battery-limited mobile devices for event detection [1]. CNNs with high accuracy …
developed in battery-limited mobile devices for event detection [1]. CNNs with high accuracy …
A reconfigurable 1T1C eDRAM-based spiking neural network computing-in-memory processor for high system-level efficiency
Spiking Neural Network (SNN) Computing-In-Memory (CIM) was proposed for high macro-
level energy efficiency. However, system-level energy efficiency is limited by EMA due to a …
level energy efficiency. However, system-level energy efficiency is limited by EMA due to a …
Unearthing the Potential of Spiking Neural Networks
Spiking neural networks (SNNs) offer a promising alternative to traditional analog neural
networks (ANNs), especially for sequential tasks, with enhanced energy efficiency. The …
networks (ANNs), especially for sequential tasks, with enhanced energy efficiency. The …