Modulo scheduling is a framework within which a wide variety of algorithms and heuristics
may be defined for software pipelining innermost loops. This paper presents a practical …

This paper presents a modular and extensible high-level synthesis research system, called
SPARK, that takes a behavioral description in ANSI-C as input and produces synthesizable …

Instruction-level parallelism (ILP) is a family of processor and compiler design techniques
that speed up execution by causing individual machine operations to execute in parallel …

Although VLIW architectures offer the advantages of simplicity of design and high issue
rates, a major impediment to their use is that they are not compatible with the existing …

Modulo scheduling is a framework within which algorithms for software pipelining innermost
loops may be defined. The framework specifies a set of constraints that must be met in order …

The widespread use of object-oriented languages and Internet security concerns are just the
beginning. Add embedded systems, multiple memory banks, highly pipelined units …

Nearly all personal computer and workstation processors, and virtually all high-performance
embedded processor cores, now embody instruction level parallel (ILP) processing in the …

Modern electronics is driven by the explosive growth of digital communications and multi-
media technology. A basic challenge is to design first-time-right complex digital systems, that …

Rapid advances in microelectronic integration and the advent of Systems-on-Chip have
fueled the need for high-level synthesis, ie, an automated approach to the synthesis of …

A popular algorithm to compact a VLSI symbolic layout is to use a graph algorithm similar to
finding the'longest-path'in a network. The algorithm assumes that the spacing constraints on …