Co-packaged optics (CPO): status, challenges, and solutions
Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter
traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three …
traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three …
A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET
J Kim, S Kundu, A Balankutty, M Beach… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents analysis, design details, and measurement result of a 224-Gb/s four-
level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage …
level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage …
A 112.5 Gb/s ADC-DSP-based PAM-4 long-reach transceiver with> 50dB channel loss in 5nm FinFET
Z Guo, A Mostafa, A Elshazly, B Chen… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
With increasing demand in next-generation data centers and high-performance computing
and networking, wireline transceivers are required to operate at 112Gb/s to provide high …
and networking, wireline transceivers are required to operate at 112Gb/s to provide high …
Beyond CPO: a motivation and approach for bringing optics onto the silicon interposer
Co-packaged optics (CPO) technology is well positioned to break through the bottlenecks
that impede efficient bandwidth scaling in key near-term commercial integrated circuits. We …
that impede efficient bandwidth scaling in key near-term commercial integrated circuits. We …
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-based SerDes receiver with hybrid AFE capable of supporting long reach channels
A Khairi, Y Krupnik, A Laufer, Y Segal… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is
implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front …
implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front …
A 4.63 pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET
H Park, M Abdullatif, E Chen, A Elmallah… - … Solid-State Circuits …, 2023 - ieeexplore.ieee.org
In hyper scale data centers, high-speed links beyond 100Gb/s are required by applications
such as XSR (co-packaged optics and die-to-die interconnects) or LR (ethernet switches …
such as XSR (co-packaged optics and die-to-die interconnects) or LR (ethernet switches …
A 4.5 X noise improved split-resistance currennt mode bandgap with 18.4 ppm/° C in 28nm CMOS
R Nagulapalli, RK Palani - 2023 34th Irish Signals and Systems …, 2023 - ieeexplore.ieee.org
This paper presents a technique to limit the noise multiplication of operational amplifier used
in the bandgap core without adding any extra component. This is achieved by shifting the …
in the bandgap core without adding any extra component. This is achieved by shifting the …
An output bandwidth optimized 200-Gb/s PAM-4 100-Gb/s NRZ transmitter with 5-tap FFE in 28-nm CMOS
This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-
Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the …
Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the …
A 112-Gb/s PAM-4 low-power nine-tap sliding-block DFE in a 7-nm FinFET wireline receiver
J Bailey, H Shakiba, E Nir, G Marderfeld… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
Practical realization of decision feedback equalizers (DFEs) has to date been limited to at
most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power …
most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power …
A low-jitter ring-DCO-based fractional-N digital PLL with a 1/8 DTC-range-reduction technique using a quadruple-timing-margin phase selector
This work presents a fractional-ring-oscillator (RO)-based digital phase-locked loop (DPLL).
To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant …
To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant …